Low Pass Filter Circuit with Enhanced Step Response

Low Pass Filter Circuit with Enhanced Step Response

Effect on the system’s time-domain response is a common problem when designing low-pass filters. The system may fail to recognize significant changes in time because pushing the cut-off frequency lower slows the step response. For solving the problem, this is the figure of the circuit.


On this circuit diagram, lower cut-off frequency is allowed without sacrificing the step-response time. The delta (difference) between the filter’s input and output is monitored by window comparator. The filter increases its slew rate by increasing its cut-off frequency an order of magnitude when the delta exceeds 50mV. Low-pass-filtered by R4 and C3 is the original signal which is producing a cut-off frequency (312Hz) that reduces sensitivity to momentary glitches. The window-comparator input is drove by the filtered input. Comparator U2A or U2B will assert its output low if the input is outside the 50mV window. The low output drives Q5 into cutoff, causing its collector to presume a high impedance.

The filter’s cutoff frequency increases by ten times because the Q5 collector no longer grounds capacitor C2. The cutoff frequency throttles back to its quiescent state. When the system output changes to within 50mV of the system input. This circuit diagram is configured for very low cutoff frequency, but changing C1 and C2 can rescale the configuration to higher frequency, where the oscillation frequency fOSC (in kHz) is 30 x 103/COSC (in pF) and the cutoff frequency is fOSC/100. For different window values in which the delta equals the resistance multiplied by 115µA, we can modify R2 and R3. The type of comparator must be an open-drain type.

[Source: maxim-ic.com]