Sunday 15 January 2012

Pin Configuration of IC's and Semiconductors: LM110, LM210, LM310 Voltage Follower

Pin Configuration of IC's and Semiconductors: LM110, LM210, LM310 Voltage Follower: LM110/LM210/LM310 Voltage Follower

Pin Configuration of IC's and Semiconductors: PIC18F2455, PIC18F2550, PIC18F4455, PIC18F4550

Pin Configuration of IC's and Semiconductors: PIC18F2455, PIC18F2550, PIC18F4455, PIC18F4550: High-Performance, Enhanced Flash USB Microcontrollers with nanoWatt Technology

Transistor pin configruation and packages



NPN;TRANSISTOR
BC107 BC108 BC109 BFX84 BFY50  2N706 2N2369  BC286  BF180  BF181  BF182  BF183  BF200 BF115 BF167 BF173  BF185 BF185 2N3055 BDY20 BD121 BD123 AD161 BD135 BD131 D437 BUP41 AC176 AC187 BC182 BC183 BC184 2N3707 2N3710 BF194 BF195 BF196
BF197 BC157 BC158 BC159 BCX35 BD539 BD743 TIP29C BU407 BUP30 2N6099 BD243C D44C10 BD241C


PNP;TRANSISTOR
BD540 BD744 TIP30C BD244C BD240C BD242C BFR14 BFR49 BC846B BC847B BC848B BC849B  BC856B BC857B BC858B BC859B BC147 BC148 BC149 BCX31 BD136  BD132
BD438 PNP3055  BDX18 OC26 AD149 AD162 AF124 AF125 AF126 AF127 AF139 AF178
AF179 AF180 AF181 BC177 BC178 BC186 BC187 BFX88 BCY71 BC287  2N2904  BC212
BC213  BC214 2N3702 2N3703 AC128 AC188


UNIJUNCTION
2N2646  2N2647 2N4870


FET
3N140 3N141 40673 BF256 2N3819 BF960 BF961 BF981 3SK81 2N4871

LM35 Temperature Sensor

LM35 Sensor Specification

The LM35 series are precision integrated-circuit LM35 temperature sensors, whose output voltage is linearly proportional to the Celsius (Centigrade) temperature. The LM35 sensor thus has an advantage over linear temperature sensors calibrated in ° Kelvin, as the user is not required to subtract a large constant voltage from its output to obtain convenient Centigrade scaling. The LM35 sensor does not require any external calibration or trimming to provide typical accuracies of ±¼°C at room temperature and ±¾°C over a full -55 to +150°C temperature range. Low cost is assured by trimming and calibration at the wafer level. The LM35's low output impedance, linear output, and precise inherent calibration make interfacing to readout or control circuitry especially easy. It can be used with single power supplies, or with plus and minus supplies. As it draws only 60 µA from its supply, it has very low self-heating, less than 0.1°C in still air. The LM35 is rated to operate over a -55° to +150°C temperature range, while the LM35C sensor is rated for a -40° to +110°C range (-10° with improved accuracy). The LM35 series is available packaged in hermetic TO-46 transistor packages, while the LM35C, LM35CA, and LM35D are also available in the plastic TO-92 transistor package. The LM35D sensor is also available in an 8-lead surface mount small outline package and a plastic TO-220 package.

EPROM, PROM 27xxxx, 27xx, 27xxx Series

EPROM, PROM 27xxxx, 27xx, 27xxx Series Memory Chips


2708

1kx8 EPROM.
Requires -5, +5 and +12V.
    +-----+--+-----+
 A7 |1    +--+   24| VCC
 A6 |2           23| A8
 A5 |3           22| A9
 A4 |4           21| VEE
 A3 |5           20| /CE
 A2 |6           19| VDD
 A1 |7    2708   18| PRGM
 A0 |8           17| D7
 D0 |9           16| D6
 D1 |10          15| D5
 D2 |11          14| D4
GND |12          13| D3
    +--------------+

2716

2kx8 EPROM.
    +-----+--+-----+
 A7 |1    +--+   24| VCC
 A6 |2           23| A8
 A5 |3           22| A9
 A4 |4           21| VPP
 A3 |5           20| /OE
 A2 |6           19| A10
 A1 |7    2716   18| /CE
 A0 |8           17| D7
 D0 |9           16| D6
 D1 |10          15| D5
 D2 |11          14| D4
GND |12          13| D3
    +--------------+

2732

4kx8 EPROM.
    +-----+--+-----+
 A7 |1    +--+   24| VCC
 A6 |2           23| A8
 A5 |3           22| A9
 A4 |4           21| A11
 A3 |5           20| /OE VPP
 A2 |6    2732   19| A10
 A1 |7           18| /CE
 A0 |8           17| D7
 D0 |9           16| D6
 D1 |10          15| D5
 D2 |11          14| D4
GND |12          13| D3
    +--------------+


2764

8kx8 EPROM.
Available in 300 and 600 mil packages.
    +-----+--+-----+
VPP |1    +--+   28| VCC
A12 |2           27| /PGM
 A7 |3           26|
 A6 |4           25| A8
 A5 |5           24| A9
 A4 |6           23| A11
 A3 |7    2764   22| /OE
 A2 |8           21| A10
 A1 |9           20| /CE
 A0 |10          19| D7
 D0 |11          18| D6
 D1 |12          17| D5
 D2 |13          16| D4
GND |14          15| D3
    +--------------+

27128

16kx8 EPROM.
Available in 300 and 600 mil packages.
    +-----+--+-----+
VPP |1    +--+   28| VCC
A12 |2           27| /PGM
 A7 |3           26| A13
 A6 |4           25| A8
 A5 |5           24| A9
 A4 |6           23| A11
 A3 |7   27128   22| /OE
 A2 |8           21| A10
 A1 |9           20| /CE
 A0 |10          19| D7
 D0 |11          18| D6
 D1 |12          17| D5
 D2 |13          16| D4
GND |14          15| D3
    +--------------+

27256

32kx8 EPROM.
Available in 300 and 600 mil packages.
    +-----+--+-----+
VPP |1    +--+   28| VCC
A12 |2           27| A14
 A7 |3           26| A13
 A6 |4           25| A8
 A5 |5           24| A9
 A4 |6           23| A11
 A3 |7   27256   22| /OE
 A2 |8           21| A10
 A1 |9           20| /CE
 A0 |10          19| D7
 D0 |11          18| D6
 D1 |12          17| D5
 D2 |13          16| D4
GND |14          15| D3
    +--------------+

27512

64kx8 EPROM.
Available in 300 and 600 mil packages.
    +-----+--+-----+
A15 |1    +--+   28| VCC
A12 |2           27| A14
 A7 |3           26| A13
 A6 |4           25| A8
 A5 |5           24| A9
 A4 |6           23| A11
 A3 |7   27512   22| /OE VPP
 A2 |8           21| A10
 A1 |9           20| /CE
 A0 |10          19| D7
 D0 |11          18| D6
 D1 |12          17| D5
 D2 |13          16| D4
GND |14          15| D3
    +--------------+

271001

128kx8 EPROM.
    +-----+--+-----+
VPP |1    +--+   32| VCC
A16 |2           31| /PGM
A15 |3           30|
A12 |4           29| A14
 A7 |5           28| A13
 A6 |6           27| A8
 A5 |7           26| A9
 A4 |8   271001  25| A11
 A3 |9           24| /OE
 A2 |10          23| A10
 A1 |11          22| /CE
 A0 |12          21| D7
 D0 |13          20| D6
 D1 |14          19| D5
 D2 |15          18| D4
GND |16          17| D3
    +--------------+

271024

64kx16 EPROM.
    +-----+--+-----+
VPP |1    +--+   40| VCC
/CE |2           39| /PGM
D15 |3           38|
D14 |4           37| A15
D13 |5           36| A14
D12 |6           35| A13
D11 |7           34| A12
D10 |8           33| A11
 D9 |9           32| A10
 D8 |10  271024  31| A9
GND |11          30| GND
 D7 |12          29| A8
 D6 |13          28| A7
 D5 |14          27| A6
 D4 |15          26| A5
 D3 |16          25| A4
 D2 |17          24| A3
 D1 |18          23| A2
 D0 |19          22| A1
/OE |20          21| A0
    +--------------+

272001

256kx8 EPROM.
    +-----+--+-----+
VPP |1    +--+   32| VCC
A16 |2           31| /PGM
A15 |3           30| A17
A12 |4           29| A14
 A7 |5           28| A13
 A6 |6           27| A8
 A5 |7           26| A9
 A4 |8   272001  25| A11
 A3 |9           24| /OE
 A2 |10          23| A10
 A1 |11          22| /CE
 A0 |12          21| D7
 D0 |13          20| D6
 D1 |14          19| D5
 D2 |15          18| D4
GND |16          17| D3
    +--------------+

274001

512kx8 EPROM.
    +-----+--+-----+
VPP |1    +--+   32| VCC
A16 |2           31| A18
A15 |3           30| A17
A12 |4           29| A14
 A7 |5           28| A13
 A6 |6           27| A8
 A5 |7           26| A9
 A4 |8   274001  25| A11
 A3 |9           24| /OE
 A2 |10          23| A10
 A1 |11          22| /CE
 A0 |12          21| D7
 D0 |13          20| D6
 D1 |14          19| D5
 D2 |15          18| D4
GND |16          17| D3
    +--------------+
7400 series TTL IC 74300--74399
74300-74400 74LSxxx, 74HCxxx, 74AHCxxx, 74Fxxx, 74ALSxxx, 54xxxx


74303

8-line inverting/noninverting divide by 2 clock driver.
Six outputs in phase with CLK, two out of phase.
    +---+--+---+
 Q3 |1  +--+ 16| Q2
 Q4 |2       15| Q1
GND |3       14| /RST
GND |4   74  13| VCC
GND |5  303  12| VCC
 Q5 |6       11| CLK
 Q6 |7       10| /PRE
/Q7 |8        9| /Q8
    +----------+


74304

8-line noninverting divide by 2 clock driver.
    +---+--+---+
 Q3 |1  +--+ 16| Q2
 Q4 |2       15| Q1
GND |3       14| /RST
GND |4   74  13| VCC
GND |5  304  12| VCC
 Q5 |6       11| CLK
 Q6 |7       10| /PRE
 Q7 |8        9| Q8
    +----------+

74305

8-line inverting/noninverting divide by 2 clock driver.
Four outputs in phase with CLK, four out of phase.
    +---+--+---+
 Q3 |1  +--+ 16| Q2
 Q4 |2       15| Q1
GND |3       14| /RST
GND |4   74  13| VCC
GND |5  305  12| VCC
/Q5 |6       11| CLK
/Q6 |7       10| /PRE
/Q7 |8        9| /Q8
    +----------+

74306

2-bit 3-state noninverting buffer/line driver.
     +---+--+---+            +---+---*---+
/1OE |1  +--+  8| 1Y         | A |/OE| Y |
  1A |2   74   7| VCC        +===+===*===+
 GND |3  306   6| 1A         | 0 | 0 | 0 |
/2OE |4        5| 2Y         | 1 | 0 | 1 |
     +----------+            | X | 1 | Z |
                             +---+---*---+

74322

8-bit 3-state shift register with with sign extension and selectable serial inputs. Multiplexed parallel I/O.
       +---+--+---+
   /OE |1  +--+ 20| VCC
SH//LD |2       19| E//D
     D |3       18| /SEXT
    P0 |4       17| E
    P2 |5   74  16| P1
    P4 |6  322  15| P3
    P6 |7       14| P5
   /OE |8       13| P7
  /RST |9       12| Q7
   GND |10      11| CLK
       +----------+

74323

8-bit 3-state bidirectional universal shift register with reset and multiplexed parallel I/O.
     +---+--+---+
  S0 |1  +--+ 20| VCC
/OE1 |2       19| S1
/OE2 |3       18| D
  P6 |4       17| Q7
  P4 |5   74  16| P7
  P2 |6  323  15| P5
  P0 |7       14| P3
  Q0 |8       13| P1
/RST |9       12| CLK
 GND |10      11| L
     +----------+

74328

6-line selectable phase clock driver.
    +---+--+---+
GND |1  +--+ 16| 1Y1
1Y2 |2       15| SEL1
2Y1 |3       14| VCC
GND |4   74  13| SEL2
2Y2 |5  328  12| A
3Y1 |6       11| VCC
GND |7       10| SEL3
4Y1 |8        9| SEL4
    +----------+

74329

6-line selectable phase clock driver.
    +---+--+---+
GND |1  +--+ 16| 1Y1
1Y2 |2       15| SEL1
2Y1 |3       14| VCC
GND |4   74  13| SEL2
2Y2 |5  329  12| A
3Y1 |6       11| VCC
GND |7       10| SEL3
4Y1 |8        9| SEL4
    +----------+

74330

Dual 1-line to 3-line noninverting clock driver and 1-line to 4-line noninverting divide by 2 clock driver.
     +---+--+---+
 GND |1  +--+ 24| OEQ
  Q1 |2       23| Q3
  Q2 |3       22| CLKQ
 GND |4       21| VCC
  X1 |5       20| RST
 OEX |6   74  19| X3
CLKX |7  330  18| GND
  X2 |8       17| X4
 GND |9       16| VCC
  Y1 |10      15| OEY
  Y2 |11      14| Y3
 GND |12      13| CLKY
     +----------+

74337

8-line 3-state noninverting clock driver with divide by 2 output on 4 lines.
     +---+--+---+
  Y3 |1  +--+ 20| Y2
 GND |2       19| GND
  Y4 |3       18| Y1
 VCC |4       17| VCC
 /OE |5   74  16| CLK
/RST |6  337  15| GND
 VCC |7       14| VCC
  Q1 |8       13| Q4
 GND |9       12| GND
  Q2 |10      11| Q3
     +----------+

74338

6-line noninverting clock driver with divide by 2 and PLL.
Four outputs toggle at the clock, one at one-half, one at double speed.
    +---+--+---+
GND |1  +--+ 20| /OE
 Y1 |2       19| VCC
GND |3       18| DF
 Y2 |4       17| VCC
GND |5   74  16| CLKIN
GND |6  338  15| GND
 Y3 |7       14| HF
GND |8       13| VCC
 Y4 |9       12| /RST
GND |10      11| VCC
    +----------+

74339

8-line 3-state noninverting clock driver with divide by 2 output on 4 lines.
     +---+--+---+
  Y3 |1  +--+ 20| Y2
 GND |2       19| GND
  Y4 |3       18| Y1
 VCC |4       17| VCC
 /OE |5   74  16| CLK
/RST |6  339  15| GND
 VCC |7       14| VCC
  Q1 |8       13| Q4
 GND |9       12| GND
  Q2 |10      11| Q3
     +----------+

74340

8-line inverting clock driver.
    +---+--+---+
VCC |1  +--+ 20| VCC
 E1 |2       19| Q1
 E2 |3       18| Q2
 IN |4       17| GND
 P0 |5   74  16| Q3
 P1 |6  340  15| Q4
VCC |7       14| GND
 Q8 |8       13| Q5
 Q7 |9       12| Q6
GND |10      11| GND
    +----------+

74348

8-to-3 line 3-state inverting priority encoder with cascade inputs.
    +---+--+---+
/A4 |1  +--+ 16| VCC
/A5 |2       15| /EO
/A6 |3       14| /GS
/A7 |4   74  13| /A3
/EI |5  348  12| /A2
 Y2 |6       11| /A1
 Y1 |7       10| /A0
GND |8        9| Y0
    +----------+

74352

8-to-2 line inverting data selector/multiplexer with separate enables.
     +---+--+---+
/1EN |1  +--+ 16| VCC
  S1 |2       15| /2EN
 1A3 |3       14| S0
 1A2 |4   74  13| 2A3
 1A1 |5  352  12| 2A2
 1A0 |6       11| 2A1
  1Y |7       10| 2A0
 GND |8        9| 2Y
     +----------+

74353

8-to-2 line 3-state inverting data selector/multiplexer.
     +---+--+---+
/1EN |1  +--+ 16| VCC
  S1 |2       15| /2EN
 1A3 |3       14| S0
 1A2 |4   74  13| 2A3
 1A1 |5  353  12| 2A2
 1A0 |6       11| 2A1
 /1Y |7       10| 2A0
 GND |8        9| /2Y
     +----------+


74354

8-to-1 line 3-state data selector/multiplexer with address and data latches and complementary outputs.
    +---+--+---+
 A7 |1  +--+ 20| VCC
 A6 |2       19| Y
 A5 |3       18| /Y
 A4 |4       17| OE3
 A3 |5  74   16| /OE2
 A2 |6  354  15| /OE1
 A1 |7       14| A0
 A0 |8       13| A1
DLE |9       12| A2
GND |10      11| ALE
    +----------+

74356

8-to-1 line 3-state data selector/multiplexer with address latch and data register and complementary outputs.
    +---+--+---+
 A7 |1  +--+ 20| VCC
 A6 |2       19| Y
 A5 |3       18| /Y
 A4 |4       17| OE3
 A3 |5  74   16| /OE2
 A2 |6  356  15| /OE1
 A1 |7       14| A0
 A0 |8       13| A1
DLE |9       12| A2
GND |10      11| ALE
    +----------+


74365

6-bit 3-state noninverting buffer/line driver.
     +---+--+---+            +---+---*---+
/OE1 |1  +--+ 16| VCC        |/OE| A | Y |
  A1 |2       15| /OE2       +===+===*===+
  Y1 |3       14| A6         | 1 | X | Z |
  A2 |4   74  13| Y6         | 0 | 0 | 0 |
  Y2 |5  365  12| A5         | 0 | 1 | 1 |
  A3 |6       11| Y5         +---+---*---+
  Y3 |7       10| A4
 GND |8        9| Y4
     +----------+

74366

6-bit 3-state inverting buffer/line driver.
     +---+--+---+            +---+---*---+
/OE1 |1  +--+ 16| VCC        |/OE| A |/Y |
  A1 |2       15| /OE2       +===+===*===+
 /Y1 |3       14| A6         | 1 | X | Z |
  A2 |4   74  13| /Y6        | 0 | 0 | 1 |
 /Y2 |5  366  12| A5         | 0 | 1 | 0 |
  A3 |6       11| /Y5        +---+---*---+
 /Y3 |7       10| A4
 GND |8        9| /Y4
     +----------+


74367

2/4-bit 3-state noninverting buffer/line driver.
     +---+--+---+            +---+---*---+
/1OE |1  +--+ 16| VCC        |/OE| A | Y |
 1A1 |2       15| /2OE       +===+===*===+
 1Y1 |3       14| 2A2        | 1 | X | Z |
 1A2 |4   74  13| 2Y2        | 0 | 0 | 0 |
 1Y2 |5  367  12| 2A1        | 0 | 1 | 1 |
 1A3 |6       11| 2Y1        +---+---*---+
 1Y3 |7       10| 1A4
 GND |8        9| 1Y4
     +----------+

74368

2/4-bit 3-state inverting buffer/line driver.
     +---+--+---+            +---+---*---+
/1OE |1  +--+ 16| VCC        |/OE| A |/Y |
 1A1 |2       15| /2OE       +===+===*===+
/1Y1 |3       14| 2A2        | 1 | X | Z |
 1A2 |4   74  13| /2Y2       | 0 | 0 | 1 |
/1Y2 |5  368  12| 2A1        | 0 | 1 | 0 |
 1A3 |6       11| /2Y1       +---+---*---+
/1Y3 |7       10| 1A4
 GND |8        9| /1Y4
     +----------+


74373

8-bit 3-state transparent latch.
    +---+--+---+             +---+---+---*---+
/OE |1  +--+ 20| VCC         |/OE| LE| D | Q |
 Q1 |2       19| Q8          +===+===+===*===+
 D1 |3       18| D8          | 1 | X | X | Z |
 D2 |4       17| D7          | 0 | 0 | X | - |
 Q2 |5   74  16| Q7          | 0 | 1 | 0 | 0 |
 Q3 |6  373  15| Q6          | 0 | 1 | 1 | 1 |
 D3 |7       14| D6          +---+---+---*---+
 D4 |8       13| D5
 Q4 |9       12| Q5
GND |10      11| LE
    +----------+

74374

8-bit 3-state D flip-flop.
    +---+--+---+             +---+---+---*---+
/OE |1  +--+ 20| VCC         |/OE|CLK| D | Q |
 Q1 |2       19| Q8          +===+===+===*===+
 D1 |3       18| D8          | 1 | X | X | Z |
 D2 |4       17| D7          | 0 | / | 0 | 0 |
 Q2 |5   74  16| Q7          | 0 | / | 1 | 1 |
 Q3 |6  374  15| Q6          | 0 |!/ | X | - |
 D3 |7       14| D6          +---+---+---*---+
 D4 |8       13| D5
 Q4 |9       12| Q5
GND |10      11| CLK
    +----------+


74375

Dual 2-bit transparent latches with complementary outputs.
     +---+--+---+
 1D1 |1  +--+ 16| VCC
/1Q1 |2       15| 2D1
 1Q1 |3       14| /2Q1
 1LE |4   74  13| 2Q1
 1Q2 |5  375  12| 2LE
/1Q2 |6       11| 2Q2
 1D2 |7       10| /2Q2
 GND |8        9| 2D2
     +----------+

74376

4-bit J-/K flip-flop with reset.
     +---+--+---+            +---+---+---+----*---+---+
/RST |1  +--+ 16| VCC        | J |/K |CLK|/RST| Q |/Q |
  J1 |2       15| J4         +===+===+===+====*===+===+
 /K1 |3       14| /K4        | X | X | X |  0 | 0 | 1 |
  Q1 |4   74  13| Q4         | 0 | 0 | / |  1 | 0 | 1 |
  Q2 |5  376  12| Q3         | 0 | 1 | / |  1 | - | - |
 /K2 |6       11| /K3        | 1 | 0 | / |  1 |/Q | Q |
  J2 |7       10| J3         | 1 | 1 | / |  1 | 1 | 0 |
 GND |8        9| CLK        | X | X |!/ |  1 | - | - |
     +----------+            +---+---+---+----*---+---+


74377

8-bit D flip-flop with clock enable.
       +---+--+---+          +----+---+---*---+
/CLKEN |1  +--+ 20| VCC      |/CEN|CLK| D | Q |
    Q1 |2       19| Q8       +====+===+===*===+
    D1 |3       18| D8       |  1 | X | X | - |
    D2 |4       17| D7       |  0 | / | 0 | 0 |
    Q2 |5   74  16| Q7       |  0 | / | 1 | 1 |
    Q3 |6  377  15| Q6       |  0 |!/ | X | - |
    D3 |7       14| D6       +----+---+---*---+
    D4 |8       13| D5
    Q4 |9       12| Q5
   GND |10      11| CLK
       +----------+

74378

6-bit D flip-flop with clock enable.
       +---+--+---+          +----+---+---*---+
/CLKEN |1  +--+ 16| VCC      |/CEN|CLK| D | Q |
    Q1 |2       15| Q6       +====+===+===*===+
    D1 |3       14| D6       |  1 | X | X | - |
    D2 |4   74  13| D5       |  0 | / | 0 | 0 |
    Q2 |5  378  12| Q5       |  0 | / | 1 | 1 |
    D3 |6       11| D4       |  0 |!/ | X | - |
    Q3 |7       10| Q4       +----+---+---*---+
   GND |8        9| CLK
       +----------+


74379

6-bit D flip-flop with clock enable and complementary outputs.
       +---+--+---+          +----+---+---*---+---+
/CLKEN |1  +--+ 16| VCC      |/CEN|CLK| D | Q |/Q |
    Q1 |2       15| Q4       +====+===+===*===+===+
   /Q1 |3       14| /Q4      |  1 | X | X | - | - |
    D1 |4   74  13| D4       |  0 | / | 0 | 0 | 1 |
    D2 |5  379  12| D3       |  0 | / | 1 | 1 | 0 |
   /Q2 |6       11| /Q3      |  0 |!/ | X | - | - |
    Q2 |7       10| Q3       +----+---+---*---+---+
   GND |8        9| CLK
       +----------+

74381

4-bit 8-function arithmetic logic unit (ALU)
    +---+--+---+
 A1 |1  +--+ 20| VCC
 B1 |2       19| A2
 A0 |3       18| B2
 B0 |4       17| A3
 S0 |5   74  16| B3
 S1 |6  381  15| CIN
 S2 |7       14| /P
 F0 |8       13| /G
 F1 |9       12| F3
GND |10      11| F2
    +----------+


74382

4-bit 8-function arithmetic logic unit (ALU) with ripple carry and overflow outputs.
    +---+--+---+
 A1 |1  +--+ 20| VCC
 B1 |2       19| A2
 A0 |3       18| B2
 B0 |4       17| A3
 S0 |5   74  16| B3
 S1 |6  382  15| CIN
 S2 |7       14| COUT
 F0 |8       13| OVR
 F1 |9       12| F3
GND |10      11| F2
    +----------+

74385

Quad serial adder/subtractor.
Contains four independent adder/subtractor elements with common clock and carry reset.
      +---+--+---+
  CLK |1  +--+ 20| VCC
   1S |2       19| 4S
1S//A |3       18| 4S//A
   1B |4       17| 4B
   1A |5   74  16| 4A
   2A |6  385  15| 3A
   2B |7       14| 3B
2S//A |8       13| 3S//A
   2S |9       12| 3S
  GND |10      11| RST
      +----------+

74386

Quad 2-input XOR gates.
    +---+--+---+             +---+---*---+                    _   _
 1A |1  +--+ 14| VCC         | A | B | Y |       Y = A$B = (A.B)+(A.B)
 1B |2       13| 4B          +===+===*===+
 1Y |3  74   12| 4A          | 0 | 0 | 0 |
 2Y |4  386  11| 4Y          | 0 | 1 | 1 |
 2A |5       10| 3Y          | 1 | 0 | 1 |
 2B |6        9| 3B          | 1 | 1 | 0 |
GND |7        8| 3A          +---+---*---+
    +----------+

74390

Dual 4-bit asynchronous decade counters with separate /2 and /5 sections and reset.
       +---+--+---+
/1CLK0 |1  +--+ 16| VCC
  1RST |2       15| /2CLK0
   1Q0 |3       14| 2RST
/1CLK1 |4   74  13| 2Q0
   1Q1 |5  390  12| /2CLK1
   1Q2 |6       11| 2Q1
   1Q3 |7       10| 2Q2
   GND |8        9| 2Q3
       +----------+

74393

Dual 4-bit asynchronous binary counters with reset.
      +---+--+---+
/1CLK |1  +--+ 14| VCC
 1RST |2       13| /2CLK
  1Q0 |3   74  12| 2RST
  1Q1 |4  393  11| 2Q0
  1Q2 |5       10| 2Q1
  1Q3 |6        9| 2Q2
  GND |7        8| 2Q3
      +----------+

74395

4-bit 3-state universal shift register with load and asynchronous reset.
       +---+--+---+
  /RST |1  +--+ 16| VCC
     D |2       15| Y0
    P0 |3       14| Y1
    P1 |4   74  13| Y2
    P2 |5  395  12| Y3
    P3 |6       11| Q3
LD//SH |7       10| CLK
   GND |8        9| /OE
       +----------+

74398

8-to-4 line data selector/multiplexer with output registers and complementary outputs.
    +---+--+---+
  S |1  +--+ 20| VCC
 1Y |2       19| 4Y
/1Y |3       18| /4Y
1A0 |4       17| 4A0
1A1 |5   74  16| 4A1
2A1 |6  398  15| 3A1
2A0 |7       14| 3A0
/2Y |8       13| /3Y
 2Y |9       12| 3Y
GND |10      11| CLK
    +----------+

74399

8-to-4 line inverting data selector/multiplexer with output registers.
    +---+--+---+
  S |1  +--+ 16| VCC
 1Y |2       15| 4Y
1A0 |3       14| 4A0
1A1 |4   74  13| 4A1
2A1 |5  399  12| 3A1
2A0 |6       11| 3A0
 2Y |7       10| 3Y
GND |8        9| CLK
    +----------+

7400 series TTL ICs 74200--74300

7400 series TTL ICs 74200--74300
74200-74300 74LSxxx, 74HCxxx, 74AHCxxx, 74Fxxx, 74ALSxxx, 54xxxx


74203

6-line inverting clock driver.
    +---+--+---+
 1Y |1  +--+ 20| 1A
 2Y |2       19| 2A
 3Y |3       18| 3A
GND |4       17|
GND |5   74  16| VCC
GND |6  203  15| VCC
GND |7       14|
 4Y |8       13| 4A
 5Y |9       12| 5A
 6Y |10      11| 6A
    +----------+

74204

6-line inverting clock driver.
    +---+--+---+
 1Y |1  +--+ 20| 1A
 2Y |2       19| 2A
 3Y |3       18| 3A
GND |4       17|
GND |5   74  16| VCC
GND |6  204  15| VCC
GND |7       14|
 4Y |8       13| 4A
 5Y |9       12| 5A
 6Y |10      11| 6A
    +----------+

74208

Dual 3-state 1-line to 4-line noninverting clock driver.
    +---+--+---+
1Y2 |1  +--+ 20| 1Y1
1Y3 |2       19| 1A
1Y4 |3       18| /1OE1
GND |4       17| /1OE2
GND |5   74  16| VCC
GND |6  208  15| VCC
GND |7       14| 2A
2Y1 |8       13| /2OE1
2Y2 |9       12| /2OE2
2Y3 |10      11| 2Y4
    +----------+


74209

Dual 3-state 1-line to 4-line noninverting clock driver.
    +---+--+---+
1Y2 |1  +--+ 20| 1Y1
1Y3 |2       19| 1A
1Y4 |3       18| /1OE1
GND |4       17| /1OE2
GND |5   74  16| VCC
GND |6  209  15| VCC
GND |7       14| 2A
2Y1 |8       13| /2OE1
2Y2 |9       12| /2OE2
2Y3 |10      11| 2Y4
    +----------+

74221

Dual monostable multivibrators with Schmitt-trigger inputs.
       +---+--+---+
  /1TR |1  +--+ 16| VCC
   1TR |2       15| 1RCext
 /1RST |3       14| 1Cext
   /1Q |4   74  13| 1Q
    2Q |5  221  12| /2Q
 2Cext |6       11| /2RST
2RCext |7       10| 2TR
   GND |8        9| /2TR
       +----------+


74237

1-of-8 noninverting decoder/demultiplexer with address latches.
     +---+--+---+
  S0 |1  +--+ 16| VCC
  S1 |2       15| Y0
  S2 |3       14| Y1
 /LE |4   74  13| Y2
/EN2 |5  237  12| Y3
 EN1 |6       11| Y4
  Y7 |7       10| Y5
 GND |8        9| Y6
     +----------+

74238

1-of-8 noninverting decoder/demultiplexer.
     +---+--+---+            +---+----+----+---+---+---*---+---+---+---+
  S0 |1  +--+ 16| VCC        |EN1|/EN2|/EN3| S2| S1| S0|/Y0|/Y1|...|/Y7|
  S1 |2       15| Y0         +===+====+====+===+===+===*===+===+===+===+
  S2 |3       14| Y1         | 0 | X  |  X | X | X | X | 0 | 0 | 0 | 0 |
/EN3 |4   74  13| Y2         | 1 | 1  |  X | X | X | X | 0 | 0 | 0 | 0 |
/EN2 |5  238  12| Y3         | 1 | 0  |  1 | X | X | X | 0 | 0 | 0 | 0 |
 EN1 |6       11| Y4         | 1 | 0  |  0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
  Y7 |7       10| Y5         | 1 | 0  |  0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 |
 GND |8        9| Y6         | 1 | 0  |  0 | . | . | . | 0 | 0 | . | 0 |
     +----------+            | 1 | 0  |  0 | 1 | 1 | 1 | 0 | 0 | 0 | 1 |
                             +---+----+----+---+---+---*---+---+---+---+


74239

Dual 1-of-4 noninverting decoder/demultiplexer.
     +---+--+---+            +---+---+---*---+---+---+---+
/1EN |1  +--+ 16| VCC        |/EN| S1| S0| Y0| Y1| Y2| Y3|
 1S0 |2       15| /2EN       +===+===+===*===+===+===+===+
 1S1 |3       14| 2S0        | 1 | X | X | 0 | 0 | 0 | 0 |
 1Y0 |4   74  13| 2S1        | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
 1Y1 |5  239  12| 2Y0        | 0 | 0 | 1 | 0 | 1 | 0 | 0 |
 1Y2 |6       11| 2Y1        | 0 | 1 | 0 | 0 | 0 | 1 | 0 |
 1Y3 |7       10| 2Y2        | 0 | 1 | 1 | 0 | 0 | 0 | 1 |
 GND |8        9| 2Y3        +---+---+---*---+---+---+---+
     +----------+

74240

Dual 4-bit 3-state inverting buffer/line driver.
     +---+--+---+
/1OE |1  +--+ 20| VCC
 1A1 |2       19| /2OE
/2Y4 |3       18| /1Y1
 1A2 |4       17| 2A4
/2Y3 |5  74   16| /1Y2
 1A3 |6  240  15| 2A3
/2Y2 |7       14| /1Y3
 1A4 |8       13| 2A2
/2Y1 |9       12| /1Y4
 GND |10      11| 2A1
     +----------+


74241

Dual 4-bit 3-state noninverting buffer/line driver.
One active low, one active high output enable.
     +---+--+---+
/1OE |1  +--+ 20| VCC
 1A4 |2       19| 2OE
 2Y1 |3       18| 1Y1
 1A3 |4       17| 2A4
 2Y2 |5  74   16| 1Y2
 1A2 |6  241  15| 2A3
 2Y3 |7       14| 1Y3
 1A1 |8       13| 2A2
 2Y4 |9       12| 1Y4
 GND |10      11| 2A1
     +----------+

74242

4-bit 3-state inverting bus transceiver.
Two enable pins control output enables, one active high and one active low.
     +---+--+---+
/GAB |1  +--+ 14| VCC
     |2       13| GBA
  A1 |3  74   12|
  A2 |4  242  11| B1
  A3 |5       10| B2
  A4 |6        9| B3
 GND |7        8| B4
     +----------+

74243

4-bit 3-state noninverting bus transceiver.
Two enable pins control output enables, one active high and one active low.
     +---+--+---+
/GAB |1  +--+ 14| VCC
     |2       13| GBA
  A1 |3  74   12|
  A2 |4  243  11| B1
  A3 |5       10| B2
  A4 |6        9| B3
 GND |7        8| B4
     +----------+

74244

Dual 4-bit 3-state noninverting buffer/line driver.
     +---+--+---+
/1OE |1  +--+ 20| VCC
 1A1 |2       19| /2OE
 2Y4 |3       18| 1Y1
 1A2 |4       17| 2A4
 2Y3 |5  74   16| 1Y2
 1A3 |6  244  15| 2A3
 2Y2 |7       14| 1Y3
 1A4 |8       13| 2A2
 2Y1 |9       12| 1Y4
 GND |10      11| 2A1
     +----------+

74245

8-bit 3-state noninverting bus transceiver.
Enable and direction pins control output enables.
    +---+--+---+             +---+---*---+---+
DIR |1  +--+ 20| VCC         |/EN|DIR| A | B |
 A1 |2       19| /EN         +===+===*===+===+
 A2 |3       18| B1          | 1 | X | Z | Z |
 A3 |4       17| B2          | 0 | 0 | B | Z |
 A4 |5  74   16| B3          | 0 | 1 | Z | A |
 A5 |6  245  15| B4          +---+---*---+---+
 A6 |7       14| B5
 A7 |8       13| B6
 A8 |9       12| B7
GND |10      11| B8
    +----------+

74247

Open-collector BCD to 7-segment decoder/common-anode LED driver with ripple blank input and output.
     +---+--+---+
  A1 |1  +--+ 16| VCC
  A2 |2       15| /YF
 /LT |3       14| /YG
/RBO |4  74   13| /YA
/RBI |5  247  12| /YB
  A3 |6       11| /YC
  A0 |7       10| /YD
 GND |8        9| /YE
     +----------+

74248

BCD to 7-segment decoder/common-cathode LED driver with ripple blank input and output.
     +---+--+---+
  A1 |1  +--+ 16| VCC
  A2 |2       15| YF
 /LT |3       14| YG
/RBO |4  74   13| YA
/RBI |5  248  12| YB
  A3 |6       11| YC
  A0 |7       10| YD
 GND |8        9| YE
     +----------+

74251

8-to-1 line 3-state data selector/multiplexer with complementary outputs.
    +---+--+---+
 A3 |1  +--+ 16| VCC
 A2 |2       15| A4
 A1 |3       14| A5
 A0 |4   74  13| A6
  Y |5  251  12| A7
 /Y |6       11| S0
/EN |7       10| S1
GND |8        9| S2
    +----------+

74253

8-to-2 line 3-state noninverting data selector/multiplexer.
     +---+--+---+
/1EN |1  +--+ 16| VCC
  S1 |2       15| /2EN
 1A3 |3       14| S0
 1A2 |4   74  13| 2A3
 1A1 |5  253  12| 2A2
 1A0 |6       11| 2A1
  1Y |7       10| 2A0
 GND |8        9| 2Y
     +----------+

74256

2-of-8 addressable latch with reset and enable.
     +---+--+---+            +---+----*--------------------+
  S0 |1  +--+ 16| VCC        |/EN|/RST| Function           |
  S1 |2       15| /RST       +===+====*====================+
  1D |3       14| /EN        | 0 |  0 | 2-of-8 demultiplex |
 1Q0 |4  74   13| 2D         | 0 |  1 | addressable latch  |
 1Q1 |5  256  12| 2Q3        | 1 |  0 | reset              |
 1Q2 |6       11| 2Q2        | 1 |  1 | hold               |
 1Q3 |7       10| 2Q1        +---+----*--------------------+
 GND |8        9| 2Q0
     +----------+

74257

8-to-4 line 3-state noninverting data selector/multiplexer.
    +---+--+---+
  S |1  +--+ 16| VCC
1A0 |2       15| /EN
1A1 |3       14| 4A0
 1Y |4   74  13| 4A1
2A0 |5  257  12| 4Y
2A1 |6       11| 3A0
 2Y |7       10| 3A1
GND |8        9| 3Y
    +----------+

74258

8-to-4 line 3-state inverting data selector/multiplexer.
    +---+--+---+
  S |1  +--+ 16| VCC
1A0 |2       15| /EN
1A1 |3       14| 4A0
/1Y |4   74  13| 4A1
2A0 |5  258  12| /4Y
2A1 |6       11| 3A0
/2Y |7       10| 3A1
GND |8        9| /3Y
    +----------+

74259

1-of-8 addressable latch with reset.
    +---+--+---+             +---+----*--------------------+
 S0 |1  +--+ 16| VCC         |/EN|/RST| Function           |
 S1 |2       15| /RST        +===+====*====================+
 S2 |3       14| /EN         | 0 |  0 | 1-of-8 demultiplex |
 Q0 |4   74  13| D           | 0 |  1 | addressable latch  |
 Q1 |5  259  12| Q7          | 1 |  0 | reset              |
 Q2 |6       11| Q6          | 1 |  1 | hold               |
 Q3 |7       10| Q5          +---+----*--------------------+
GND |8        9| Q4
    +----------+

74260

Dual 5-input NOR gates.
    +---+--+---+                 ___________
 1A |1  +--+ 14| VCC         Y = (A+B+C+D+E)
 1B |2       13| 2D
 1E |3   74  12| 2C
 1C |4  260  11| 2E
 1D |5       10| 2B
/1Y |6        9| 2A
GND |7        8| /2Y
    +----------+

74265

Dual buffer/inverter plus dual AND/NAND gates.
    +---+--+---+
 1A |1  +--+ 16| VCC         1Y=1A
 1Y |2       15| 4A
/1Y |3       14| 4Y          2Y=2A.2B
 2A |4   74  13| /4Y
 2B |5  265  12| 3B          3Y=3A.3B
 2Y |6       11| 3A
/2Y |7       10| 3Y          4Y=4A
GND |8        9| /3Y
    +----------+

74266

Quad 2-input open-collector XNOR gates.
    +---+--+---+             +---+---*---+          _     _ _
 1A |1  +--+ 14| VCC         | A | B |/Y |     Y = A$B = (A.B)+(A.B)
 1B |2       13| 4B          +===+===*===+
/1Y |3  74   12| 4A          | 0 | 0 | Z |
 2A |4  266  11| /4Y         | 0 | 1 | 0 |
 2B |5       10| 3B          | 1 | 0 | 0 |
/2Y |6        9| 3A          | 1 | 1 | Z |
GND |7        8| /3Y         +---+---*---+
    +----------+

74273

8-bit 3-state D flip-flop with reset.
     +---+--+---+            +----+---+---*---+
/RST |1  +--+ 20| VCC        |/RST|CLK| D | Q |
  1Q |2       19| 8Q         +====+===+===*===+
  1D |3       18| 8D         |  0 | X | X | 0 |
  2D |4       17| 7D         |  1 | / | 0 | 0 |
  2Q |5   74  16| 7Q         |  1 | / | 1 | 1 |
  3Q |6  273  15| 6Q         +----+---+---*---+
  3D |7       14| 6D
  4D |8       13| 5D
  4Q |9       12| 5Q
 GND |10      11| CLK
     +----------+

74276

Quad J-K and J-/K flip-flops with common set and reset.
      +---+--+---+
 /RST |1  +--+ 20| VCC
   1J |2       19| 4J
/1CLK |3       18| /4CLK
  /1K |4       17| 4K
   1Q |5   74  16| 4Q
   2Q |6  276  15| 3Q
  /2K |7       14| /3K
/2CLK |8       13| /3CLK
   2J |9       12| 3J
  GND |10      11| /SET
      +----------+

74279

Quad /S-/R latches.
     +---+--+---+
 /1R |1  +--+ 16| VCC
/1S1 |2       15| /4S
/1S2 |3       14| /4R
  1Q |4   74  13| 4Q
 /2R |5  279  12| /3S2
 /2S |6       11| /3S1
  2Q |7       10| /3R
 GND |8        9| 3Q
     +----------+

74280

9-bit odd/even parity generator/checker.
      +---+--+---+
   A0 |1  +--+ 14| VCC
   A1 |2       13| A8
      |3   74  12| A7
   A2 |4  280  11| A6
 EVEN |5       10| A5
  ODD |6        9| A4
  GND |7        8| A3
      +----------+

74283

4-bit binary full adder with fast carry.
    +---+--+---+
 S2 |1  +--+ 16| VCC         S=A+B+CIN
 B2 |2       15| B3
 A2 |3       14| A3
 S1 |4   74  13| S3
 A1 |5  283  12| A4
 B1 |6       11| B4
CIN |7       10| S4
GND |8        9| COUT
    +----------+

74285

4-bit binary multiplier with open-collector outputs.
    +---+--+---+
 2C |1  +--+ 16| VCC
 2B |2       15| 2D
 2A |3       14| /GA
 1D |4   74  13| /GB
 1A |5  285  12| Y0
 1B |6       11| Y1
 1C |7       10| Y2
GND |8        9| Y3
    +----------+

74286

9-bit odd/even parity generator/checker with bus driver parity I/O port.
      +---+--+---+
   A0 |1  +--+ 14| VCC
   A1 |2       13| A8
/XMIT |3   74  12| A7
   A2 |4  286  11| A6
ERROR |5       10| A5
 PI/O |6        9| A4
  GND |7        8| A3
      +----------+

74290

4-bit asynchronous decade counter with /2 and /5 sections, set(9) and reset.
     +---+--+---+
SET1 |1  +--+ 14| VCC
     |2       13| RST2
SET2 |3   74  12| RST1
  Q2 |4  290  11| /CLK1
  Q1 |5       10| /CLK0
     |6        9| Q0
 GND |7        8| Q3
     +----------+

74292

15-bit programmable frequency divider/digital timer.
Digitally programmable from 2^2 to 2^15.
     +---+--+---+
  S1 |1  +--+ 16| VCC
  S4 |2       15| S2
 TP1 |3       14| S3
CLK1 |4  74   13| TP3
CLK2 |5  292  12|
 TP2 |6       11| /RST
   Q |7       10| S0
 GND |8        9|
     +----------+

74293

4-bit asynchronous binary counter with /2 and /8 sections and reset.
     +---+--+---+
     |1  +--+ 14| VCC
     |2       13| RST2
     |3       12| RST1
  Q2 |4  74   11| /CLK1
  Q1 |5  293  10| /CLK0
     |6        9| Q0
 GND |7        8| Q3
     +----------+

74294

15-bit programmable frequency divider/digital timer.
Digitally programmable from 2^2 to 2^15.
     +---+--+---+
  S1 |1  +--+ 16| VCC
  S0 |2       15| S2
  TP |3       14| S3
CLK1 |4  74   13|
CLK2 |5  294  12|
     |6       11| /RST
   Q |7       10|
 GND |8        9|
     +----------+

74295

4-bit 3-state negative-edge-triggered universal shift register.
       +---+--+---+
     D |1  +--+ 14| VCC
    P0 |2       13| Y0
    P1 |3       12| Y1
    P2 |4  74   11| Y2
    P3 |5  295  10| Y3
LD//SH |6        9| /CLK
   GND |7        8| OE
       +----------+


74297

Digital phase-locked loop with 4-bit counter.
      +---+--+---+
   D1 |1  +--+ 16| VCC
   D0 |2       15| D2
   EN |3       14| D3
  KCP |4  74   13| PA2
 I//D |5  297  12| ECPD
 D//U |6       11| XORPD
IDout |7       10| PB
  GND |8        9| PA1
      +----------+

74298

8-to-4 line noninverting data selector/multiplexer with output registers.
    +---+--+---+
2A1 |1  +--+ 16| VCC
2A0 |2       15| 1Q
1A0 |3       14| 2Q
1A1 |4   74  13| 3Q
3A1 |5  298  12| 4Q
4A1 |6       11| CLK
4A0 |7       10| S
GND |8        9| 3A0
    +----------+


74299

8-bit 3-state bidirectional universal shift register with asynchronous reset and with separate shift left and shift right serial inputs. Multiplexed parallel I/O.
     +---+--+---+
  S0 |1  +--+ 20| VCC
/OE1 |2       19| S1
/OE2 |3       18| D
  P6 |4       17| Q7
  P4 |5   74  16| P7
  P2 |6  299  15| P5
  P0 |7       14| P3
  Q0 |8       13| P1
/RST |9       12| CLK
 GND |10      11| L
     +----------+

7400 series TTL IC 74200--74299

7400 series TTL IC 74200--74299
74200-74250 74LSxxx, 74HCxxx, 74AHCxxx, 74Fxxx, 74ALSxxx, 54xxxx


74203

6-line inverting clock driver.
    +---+--+---+
 1Y |1  +--+ 20| 1A
 2Y |2       19| 2A
 3Y |3       18| 3A
GND |4       17|
GND |5   74  16| VCC
GND |6  203  15| VCC
GND |7       14|
 4Y |8       13| 4A
 5Y |9       12| 5A
 6Y |10      11| 6A
    +----------+

74204

6-line inverting clock driver.
    +---+--+---+
 1Y |1  +--+ 20| 1A
 2Y |2       19| 2A
 3Y |3       18| 3A
GND |4       17|
GND |5   74  16| VCC
GND |6  204  15| VCC
GND |7       14|
 4Y |8       13| 4A
 5Y |9       12| 5A
 6Y |10      11| 6A
    +----------+

74208

Dual 3-state 1-line to 4-line noninverting clock driver.
    +---+--+---+
1Y2 |1  +--+ 20| 1Y1
1Y3 |2       19| 1A
1Y4 |3       18| /1OE1
GND |4       17| /1OE2
GND |5   74  16| VCC
GND |6  208  15| VCC
GND |7       14| 2A
2Y1 |8       13| /2OE1
2Y2 |9       12| /2OE2
2Y3 |10      11| 2Y4
    +----------+


74209

Dual 3-state 1-line to 4-line noninverting clock driver.
    +---+--+---+
1Y2 |1  +--+ 20| 1Y1
1Y3 |2       19| 1A
1Y4 |3       18| /1OE1
GND |4       17| /1OE2
GND |5   74  16| VCC
GND |6  209  15| VCC
GND |7       14| 2A
2Y1 |8       13| /2OE1
2Y2 |9       12| /2OE2
2Y3 |10      11| 2Y4
    +----------+

74221

Dual monostable multivibrators with Schmitt-trigger inputs.
       +---+--+---+
  /1TR |1  +--+ 16| VCC
   1TR |2       15| 1RCext
 /1RST |3       14| 1Cext
   /1Q |4   74  13| 1Q
    2Q |5  221  12| /2Q
 2Cext |6       11| /2RST
2RCext |7       10| 2TR
   GND |8        9| /2TR
       +----------+


74237

1-of-8 noninverting decoder/demultiplexer with address latches.
     +---+--+---+
  S0 |1  +--+ 16| VCC
  S1 |2       15| Y0
  S2 |3       14| Y1
 /LE |4   74  13| Y2
/EN2 |5  237  12| Y3
 EN1 |6       11| Y4
  Y7 |7       10| Y5
 GND |8        9| Y6
     +----------+

74238

1-of-8 noninverting decoder/demultiplexer.
     +---+--+---+            +---+----+----+---+---+---*---+---+---+---+
  S0 |1  +--+ 16| VCC        |EN1|/EN2|/EN3| S2| S1| S0|/Y0|/Y1|...|/Y7|
  S1 |2       15| Y0         +===+====+====+===+===+===*===+===+===+===+
  S2 |3       14| Y1         | 0 | X  |  X | X | X | X | 0 | 0 | 0 | 0 |
/EN3 |4   74  13| Y2         | 1 | 1  |  X | X | X | X | 0 | 0 | 0 | 0 |
/EN2 |5  238  12| Y3         | 1 | 0  |  1 | X | X | X | 0 | 0 | 0 | 0 |
 EN1 |6       11| Y4         | 1 | 0  |  0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
  Y7 |7       10| Y5         | 1 | 0  |  0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 |
 GND |8        9| Y6         | 1 | 0  |  0 | . | . | . | 0 | 0 | . | 0 |
     +----------+            | 1 | 0  |  0 | 1 | 1 | 1 | 0 | 0 | 0 | 1 |
                             +---+----+----+---+---+---*---+---+---+---+


74239

Dual 1-of-4 noninverting decoder/demultiplexer.
     +---+--+---+            +---+---+---*---+---+---+---+
/1EN |1  +--+ 16| VCC        |/EN| S1| S0| Y0| Y1| Y2| Y3|
 1S0 |2       15| /2EN       +===+===+===*===+===+===+===+
 1S1 |3       14| 2S0        | 1 | X | X | 0 | 0 | 0 | 0 |
 1Y0 |4   74  13| 2S1        | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
 1Y1 |5  239  12| 2Y0        | 0 | 0 | 1 | 0 | 1 | 0 | 0 |
 1Y2 |6       11| 2Y1        | 0 | 1 | 0 | 0 | 0 | 1 | 0 |
 1Y3 |7       10| 2Y2        | 0 | 1 | 1 | 0 | 0 | 0 | 1 |
 GND |8        9| 2Y3        +---+---+---*---+---+---+---+
     +----------+

74240

Dual 4-bit 3-state inverting buffer/line driver.
     +---+--+---+
/1OE |1  +--+ 20| VCC
 1A1 |2       19| /2OE
/2Y4 |3       18| /1Y1
 1A2 |4       17| 2A4
/2Y3 |5  74   16| /1Y2
 1A3 |6  240  15| 2A3
/2Y2 |7       14| /1Y3
 1A4 |8       13| 2A2
/2Y1 |9       12| /1Y4
 GND |10      11| 2A1
     +----------+


74241

Dual 4-bit 3-state noninverting buffer/line driver.
One active low, one active high output enable.
     +---+--+---+
/1OE |1  +--+ 20| VCC
 1A4 |2       19| 2OE
 2Y1 |3       18| 1Y1
 1A3 |4       17| 2A4
 2Y2 |5  74   16| 1Y2
 1A2 |6  241  15| 2A3
 2Y3 |7       14| 1Y3
 1A1 |8       13| 2A2
 2Y4 |9       12| 1Y4
 GND |10      11| 2A1
     +----------+

74242

4-bit 3-state inverting bus transceiver.
Two enable pins control output enables, one active high and one active low.
     +---+--+---+
/GAB |1  +--+ 14| VCC
     |2       13| GBA
  A1 |3  74   12|
  A2 |4  242  11| B1
  A3 |5       10| B2
  A4 |6        9| B3
 GND |7        8| B4
     +----------+

74243

4-bit 3-state noninverting bus transceiver.
Two enable pins control output enables, one active high and one active low.
     +---+--+---+
/GAB |1  +--+ 14| VCC
     |2       13| GBA
  A1 |3  74   12|
  A2 |4  243  11| B1
  A3 |5       10| B2
  A4 |6        9| B3
 GND |7        8| B4
     +----------+

74244

Dual 4-bit 3-state noninverting buffer/line driver.
     +---+--+---+
/1OE |1  +--+ 20| VCC
 1A1 |2       19| /2OE
 2Y4 |3       18| 1Y1
 1A2 |4       17| 2A4
 2Y3 |5  74   16| 1Y2
 1A3 |6  244  15| 2A3
 2Y2 |7       14| 1Y3
 1A4 |8       13| 2A2
 2Y1 |9       12| 1Y4
 GND |10      11| 2A1
     +----------+

74245

8-bit 3-state noninverting bus transceiver.
Enable and direction pins control output enables.
    +---+--+---+             +---+---*---+---+
DIR |1  +--+ 20| VCC         |/EN|DIR| A | B |
 A1 |2       19| /EN         +===+===*===+===+
 A2 |3       18| B1          | 1 | X | Z | Z |
 A3 |4       17| B2          | 0 | 0 | B | Z |
 A4 |5  74   16| B3          | 0 | 1 | Z | A |
 A5 |6  245  15| B4          +---+---*---+---+
 A6 |7       14| B5
 A7 |8       13| B6
 A8 |9       12| B7
GND |10      11| B8
    +----------+

74247

Open-collector BCD to 7-segment decoder/common-anode LED driver with ripple blank input and output.
     +---+--+---+
  A1 |1  +--+ 16| VCC
  A2 |2       15| /YF
 /LT |3       14| /YG
/RBO |4  74   13| /YA
/RBI |5  247  12| /YB
  A3 |6       11| /YC
  A0 |7       10| /YD
 GND |8        9| /YE
     +----------+

74248

BCD to 7-segment decoder/common-cathode LED driver with ripple blank input and output.
     +---+--+---+
  A1 |1  +--+ 16| VCC
  A2 |2       15| YF
 /LT |3       14| YG
/RBO |4  74   13| YA
/RBI |5  248  12| YB
  A3 |6       11| YC
  A0 |7       10| YD
 GND |8        9| YE
     +----------+

74251

8-to-1 line 3-state data selector/multiplexer with complementary outputs.
    +---+--+---+
 A3 |1  +--+ 16| VCC
 A2 |2       15| A4
 A1 |3       14| A5
 A0 |4   74  13| A6
  Y |5  251  12| A7
 /Y |6       11| S0
/EN |7       10| S1
GND |8        9| S2
    +----------+

74253

8-to-2 line 3-state noninverting data selector/multiplexer.
     +---+--+---+
/1EN |1  +--+ 16| VCC
  S1 |2       15| /2EN
 1A3 |3       14| S0
 1A2 |4   74  13| 2A3
 1A1 |5  253  12| 2A2
 1A0 |6       11| 2A1
  1Y |7       10| 2A0
 GND |8        9| 2Y
     +----------+

74256

2-of-8 addressable latch with reset and enable.
     +---+--+---+            +---+----*--------------------+
  S0 |1  +--+ 16| VCC        |/EN|/RST| Function           |
  S1 |2       15| /RST       +===+====*====================+
  1D |3       14| /EN        | 0 |  0 | 2-of-8 demultiplex |
 1Q0 |4  74   13| 2D         | 0 |  1 | addressable latch  |
 1Q1 |5  256  12| 2Q3        | 1 |  0 | reset              |
 1Q2 |6       11| 2Q2        | 1 |  1 | hold               |
 1Q3 |7       10| 2Q1        +---+----*--------------------+
 GND |8        9| 2Q0
     +----------+

74257

8-to-4 line 3-state noninverting data selector/multiplexer.
    +---+--+---+
  S |1  +--+ 16| VCC
1A0 |2       15| /EN
1A1 |3       14| 4A0
 1Y |4   74  13| 4A1
2A0 |5  257  12| 4Y
2A1 |6       11| 3A0
 2Y |7       10| 3A1
GND |8        9| 3Y
    +----------+

74258

8-to-4 line 3-state inverting data selector/multiplexer.
    +---+--+---+
  S |1  +--+ 16| VCC
1A0 |2       15| /EN
1A1 |3       14| 4A0
/1Y |4   74  13| 4A1
2A0 |5  258  12| /4Y
2A1 |6       11| 3A0
/2Y |7       10| 3A1
GND |8        9| /3Y
    +----------+

74259

1-of-8 addressable latch with reset.
    +---+--+---+             +---+----*--------------------+
 S0 |1  +--+ 16| VCC         |/EN|/RST| Function           |
 S1 |2       15| /RST        +===+====*====================+
 S2 |3       14| /EN         | 0 |  0 | 1-of-8 demultiplex |
 Q0 |4   74  13| D           | 0 |  1 | addressable latch  |
 Q1 |5  259  12| Q7          | 1 |  0 | reset              |
 Q2 |6       11| Q6          | 1 |  1 | hold               |
 Q3 |7       10| Q5          +---+----*--------------------+
GND |8        9| Q4
    +----------+

74260

Dual 5-input NOR gates.
    +---+--+---+                 ___________
 1A |1  +--+ 14| VCC         Y = (A+B+C+D+E)
 1B |2       13| 2D
 1E |3   74  12| 2C
 1C |4  260  11| 2E
 1D |5       10| 2B
/1Y |6        9| 2A
GND |7        8| /2Y
    +----------+

74265

Dual buffer/inverter plus dual AND/NAND gates.
    +---+--+---+
 1A |1  +--+ 16| VCC         1Y=1A
 1Y |2       15| 4A
/1Y |3       14| 4Y          2Y=2A.2B
 2A |4   74  13| /4Y
 2B |5  265  12| 3B          3Y=3A.3B
 2Y |6       11| 3A
/2Y |7       10| 3Y          4Y=4A
GND |8        9| /3Y
    +----------+

74266

Quad 2-input open-collector XNOR gates.
    +---+--+---+             +---+---*---+          _     _ _
 1A |1  +--+ 14| VCC         | A | B |/Y |     Y = A$B = (A.B)+(A.B)
 1B |2       13| 4B          +===+===*===+
/1Y |3  74   12| 4A          | 0 | 0 | Z |
 2A |4  266  11| /4Y         | 0 | 1 | 0 |
 2B |5       10| 3B          | 1 | 0 | 0 |
/2Y |6        9| 3A          | 1 | 1 | Z |
GND |7        8| /3Y         +---+---*---+
    +----------+

74273

8-bit 3-state D flip-flop with reset.
     +---+--+---+            +----+---+---*---+
/RST |1  +--+ 20| VCC        |/RST|CLK| D | Q |
  1Q |2       19| 8Q         +====+===+===*===+
  1D |3       18| 8D         |  0 | X | X | 0 |
  2D |4       17| 7D         |  1 | / | 0 | 0 |
  2Q |5   74  16| 7Q         |  1 | / | 1 | 1 |
  3Q |6  273  15| 6Q         +----+---+---*---+
  3D |7       14| 6D
  4D |8       13| 5D
  4Q |9       12| 5Q
 GND |10      11| CLK
     +----------+

74276

Quad J-K and J-/K flip-flops with common set and reset.
      +---+--+---+
 /RST |1  +--+ 20| VCC
   1J |2       19| 4J
/1CLK |3       18| /4CLK
  /1K |4       17| 4K
   1Q |5   74  16| 4Q
   2Q |6  276  15| 3Q
  /2K |7       14| /3K
/2CLK |8       13| /3CLK
   2J |9       12| 3J
  GND |10      11| /SET
      +----------+

74279

Quad /S-/R latches.
     +---+--+---+
 /1R |1  +--+ 16| VCC
/1S1 |2       15| /4S
/1S2 |3       14| /4R
  1Q |4   74  13| 4Q
 /2R |5  279  12| /3S2
 /2S |6       11| /3S1
  2Q |7       10| /3R
 GND |8        9| 3Q
     +----------+

74280

9-bit odd/even parity generator/checker.
      +---+--+---+
   A0 |1  +--+ 14| VCC
   A1 |2       13| A8
      |3   74  12| A7
   A2 |4  280  11| A6
 EVEN |5       10| A5
  ODD |6        9| A4
  GND |7        8| A3
      +----------+

74283

4-bit binary full adder with fast carry.
    +---+--+---+
 S2 |1  +--+ 16| VCC         S=A+B+CIN
 B2 |2       15| B3
 A2 |3       14| A3
 S1 |4   74  13| S3
 A1 |5  283  12| A4
 B1 |6       11| B4
CIN |7       10| S4
GND |8        9| COUT
    +----------+

74285

4-bit binary multiplier with open-collector outputs.
    +---+--+---+
 2C |1  +--+ 16| VCC
 2B |2       15| 2D
 2A |3       14| /GA
 1D |4   74  13| /GB
 1A |5  285  12| Y0
 1B |6       11| Y1
 1C |7       10| Y2
GND |8        9| Y3
    +----------+

74286

9-bit odd/even parity generator/checker with bus driver parity I/O port.
      +---+--+---+
   A0 |1  +--+ 14| VCC
   A1 |2       13| A8
/XMIT |3   74  12| A7
   A2 |4  286  11| A6
ERROR |5       10| A5
 PI/O |6        9| A4
  GND |7        8| A3
      +----------+

74290

4-bit asynchronous decade counter with /2 and /5 sections, set(9) and reset.
     +---+--+---+
SET1 |1  +--+ 14| VCC
     |2       13| RST2
SET2 |3   74  12| RST1
  Q2 |4  290  11| /CLK1
  Q1 |5       10| /CLK0
     |6        9| Q0
 GND |7        8| Q3
     +----------+

74292

15-bit programmable frequency divider/digital timer.
Digitally programmable from 2^2 to 2^15.
     +---+--+---+
  S1 |1  +--+ 16| VCC
  S4 |2       15| S2
 TP1 |3       14| S3
CLK1 |4  74   13| TP3
CLK2 |5  292  12|
 TP2 |6       11| /RST
   Q |7       10| S0
 GND |8        9|
     +----------+

74293

4-bit asynchronous binary counter with /2 and /8 sections and reset.
     +---+--+---+
     |1  +--+ 14| VCC
     |2       13| RST2
     |3       12| RST1
  Q2 |4  74   11| /CLK1
  Q1 |5  293  10| /CLK0
     |6        9| Q0
 GND |7        8| Q3
     +----------+

74294

15-bit programmable frequency divider/digital timer.
Digitally programmable from 2^2 to 2^15.
     +---+--+---+
  S1 |1  +--+ 16| VCC
  S0 |2       15| S2
  TP |3       14| S3
CLK1 |4  74   13|
CLK2 |5  294  12|
     |6       11| /RST
   Q |7       10|
 GND |8        9|
     +----------+

74295

4-bit 3-state negative-edge-triggered universal shift register.
       +---+--+---+
     D |1  +--+ 14| VCC
    P0 |2       13| Y0
    P1 |3       12| Y1
    P2 |4  74   11| Y2
    P3 |5  295  10| Y3
LD//SH |6        9| /CLK
   GND |7        8| OE
       +----------+


74297

Digital phase-locked loop with 4-bit counter.
      +---+--+---+
   D1 |1  +--+ 16| VCC
   D0 |2       15| D2
   EN |3       14| D3
  KCP |4  74   13| PA2
 I//D |5  297  12| ECPD
 D//U |6       11| XORPD
IDout |7       10| PB
  GND |8        9| PA1
      +----------+

74298

8-to-4 line noninverting data selector/multiplexer with output registers.
    +---+--+---+
2A1 |1  +--+ 16| VCC
2A0 |2       15| 1Q
1A0 |3       14| 2Q
1A1 |4   74  13| 3Q
3A1 |5  298  12| 4Q
4A1 |6       11| CLK
4A0 |7       10| S
GND |8        9| 3A0
    +----------+


74299

8-bit 3-state bidirectional universal shift register with asynchronous reset and with separate shift left and shift right serial inputs. Multiplexed parallel I/O.
     +---+--+---+
  S0 |1  +--+ 20| VCC
/OE1 |2       19| S1
/OE2 |3       18| D
  P6 |4       17| Q7
  P4 |5   74  16| P7
  P2 |6  299  15| P5
  P0 |7       14| P3
  Q0 |8       13| P1
/RST |9       12| CLK
 GND |10      11| L
     +----------+

Pinouts of IC and Electronic Devices

7400 series TTL IC 74150--74199

7400 series TTL IC 74150--74199
74149-74200 74LSxxx, 74HCxxx, 74AHCxxx, 74Fxxx, 74ALSxxx, 54xxxx


74150

16-to-1 line inverting data selector/multiplexer.
    +---+--+---+
 D7 |1  +--+ 24| VCC
 D6 |2       23| D8
 D5 |3       22| D9
 D4 |4       21| D10
 D3 |5       20| D11
 D2 |6   74  19| D12
 D1 |7  150  18| D13
 D0 |8       17| D14
/EN |9       16| D15
 /Y |10      15| S0
 S3 |11      14| S1
GND |12      13| S2
    +----------+

74151

8-to-1 line data selector/multiplexer with complementary outputs.
    +---+--+---+
 D3 |1  +--+ 16| VCC
 D2 |2       15| D4
 D1 |3       14| D5
 D0 |4   74  13| D6
  Y |5  151  12| D7
 /Y |6       11| S0
/EN |7       10| S1
GND |8        9| S2
    +----------+

74152

8-to-1 line inverting data selector/multiplexer.
    +---+--+---+
 A4 |1  +--+ 14| VCC
 A3 |2       13| A5
 A2 |3   74  12| A6
 A1 |4  152  11| A7
 A0 |5       10| S0
 /Y |6        9| S1
GND |7        8| S1
    +----------+


74153

8-to-2 line noninverting data selector/multiplexer with separate enables.
     +---+--+---+
/1EN |1  +--+ 16| VCC
  S1 |2       15| /2EN
 1A3 |3       14| S0
 1A2 |4   74  13| 2A3
 1A1 |5  153  12| 2A2
 1A0 |6       11| 2A1
  1Y |7       10| 2A0
 GND |8        9| 2Y
     +----------+

74154

1-of-16 inverting decoder/demultiplexer.
     +---+--+---+
 /Y0 |1  +--+ 24| VCC
 /Y1 |2       23| S0
 /Y2 |3       22| S1
 /Y3 |4       21| S2
 /Y4 |5       20| S3
 /Y5 |6   74  19| /EN2
 /Y6 |7  154  18| /EN1
 /Y7 |8       17| /Y15
 /Y8 |9       16| /Y14
 /Y9 |10      15| /Y13
/Y10 |11      14| /Y12
 GND |12      13| /Y11
     +----------+


74155

2-of-8 inverting decoder/demultiplexer with separate enables.
      +---+--+---+
 1EN1 |1  +--+ 16| VCC
/1EN2 |2       15| /2EN1
   S1 |3       14| /2EN2
 /1Y3 |4   74  13| S0
 /1Y2 |5  155  12| /2Y3
 /1Y1 |6       11| /2Y2
 /1Y0 |7       10| /2Y1
  GND |8        9| /2Y0
      +----------+

74156

2-of-8 open-collector inverting decoder/demultiplexer with separate enables.
      +---+--+---+
 1EN1 |1  +--+ 16| VCC
/1EN2 |2       15| /2EN1
   S1 |3       14| /2EN2
 /1Y3 |4   74  13| S0
 /1Y2 |5  156  12| /2Y3
 /1Y1 |6       11| /2Y2
 /1Y0 |7       10| /2Y1
  GND |8        9| /2Y0
      +----------+


74157

4-of-8 noninverting decoder/demultiplexer.
    +---+--+---+
  S |1  +--+ 16| VCC
1A0 |2       15| /EN
1A1 |3       14| 4A0
 1Y |4   74  13| 4A1
2A0 |5  157  12| 4Y
2A1 |6       11| 3A0
 2Y |7       10| 3A1
GND |8        9| 3Y
    +----------+

74158

4-of-8 inverting decoder/demultiplexer.
    +---+--+---+
  S |1  +--+ 16| VCC
1A0 |2       15| /EN
1A1 |3       14| 4A0
/1Y |4   74  13| 4A1
2A0 |5  158  12| /4Y
2A1 |6       11| 3A0
/2Y |7       10| 3A1
GND |8        9| /3Y
    +----------+


74159

1-of-16 open-collector inverting decoder/demultiplexer.
     +---+--+---+
 /Y0 |1  +--+ 24| VCC
 /Y1 |2       23| S0
 /Y2 |3       22| S1
 /Y3 |4       21| S2
 /Y4 |5       20| S3
 /Y5 |6   74  19| /EN2
 /Y6 |7  159  18| /EN1
 /Y7 |8       17| /Y15
 /Y8 |9       16| /Y14
 /Y9 |10      15| /Y13
/Y10 |11      14| /Y12
 GND |12      13| /Y11
     +----------+

74160

4-bit synchronous decade counter with load, asynchronous reset, and ripple carry output.
     +---+--+---+
/RST |1  +--+ 16| VCC
 CLK |2       15| RCO
  P0 |3       14| Q0
  P1 |4   74  13| Q1
  P2 |5  160  12| Q2
  P3 |6       11| Q3
 ENP |7       10| ENT
 GND |8        9| /LOAD
     +----------+


74161

4-bit synchronous binary counter with load, asynchronous reset, and ripple carry output.
     +---+--+---+
/RST |1  +--+ 16| VCC
 CLK |2       15| RCO
  P0 |3       14| Q0
  P1 |4   74  13| Q1
  P2 |5  161  12| Q2
  P3 |6       11| Q3
 ENP |7       10| ENT
 GND |8        9| /LOAD
     +----------+

74162

4-bit synchronous decade counter with load, reset, and ripple carry output.
     +---+--+---+
/RST |1  +--+ 16| VCC
 CLK |2       15| RCO
  P0 |3       14| Q0
  P1 |4   74  13| Q1
  P2 |5  162  12| Q2
  P3 |6       11| Q3
 ENP |7       10| ENT
 GND |8        9| /LOAD
     +----------+


74163

4-bit synchronous binary counter with load, reset, and ripple carry output.
     +---+--+---+
/RST |1  +--+ 16| VCC
 CLK |2       15| RCO
  P0 |3       14| Q0
  P1 |4   74  13| Q1
  P2 |5  163  12| Q2
  P3 |6       11| Q3
 ENP |7       10| ENT
 GND |8        9| /LOAD
     +----------+

74164

8-bit serial-in parallel-out shift register with asynchronous reset and two AND gated serial inputs.
    +---+--+---+
  D |1  +--+ 14| VCC
  E |2       13| Q7
 Q0 |3   74  12| Q6
 Q1 |4  164  11| Q5
 Q2 |5       10| Q4
 Q3 |6        9| /RST
GND |7        8| CLK
    +----------+


74165

8-bit parallel-in serial-out shift register with asynchronous parallel load and two OR gated clock inputs.
       +---+--+---+
SH//LD |1  +--+ 16| VCC
  CLK1 |2       15| CLK2
    P4 |3       14| P3
    P5 |4   74  13| P2
    P6 |5  165  12| P1
    P7 |6       11| P0
   /Q7 |7       10| D
   GND |8        9| Q7
       +----------+

74166

8-bit parallel-in serial-out shift register with asynchronous reset and two OR gated clock inputs.
     +---+--+---+
   D |1  +--+ 16| VCC
  P0 |2       15| SH//LD
  P1 |3       14| P7
  P2 |4   74  13| Q7
  P3 |5  166  12| P6
CLK1 |6       11| P5
CLK2 |7       10| P4
 GND |8        9| /RST
     +----------+


74167

4-bit synchronous decade rate multiplier.
Can perform fixed-rate or variable-rate frequency division. Output frequency is equal to input frequency multiplied by the rate input M and divided by 10.
      +---+--+---+
      |1  +--+ 16| VCC
   B2 |2       15| B1
   B3 |3       14| B0
SET-9 |4   74  13| RST
    Z |5  167  12| U/CAS
    Y |6       11| ENin
ENout |7       10| STRB
  GND |8        9| CLK
      +----------+

74168

4-bit synchronous decade up/down counter with load and ripple carry output.
     +---+--+---+
U//D |1  +--+ 16| VCC
 CLK |2       15| /RCO
  P0 |3       14| Q0
  P1 |4   74  13| Q1
  P2 |5  168  12| Q2
  P3 |6       11| Q3
/ENP |7       10| /ENT
 GND |8        9| /LOAD
     +----------+

74169

4-bit synchronous binary up/down counter with load and ripple carry output.
     +---+--+---+
U//D |1  +--+ 16| VCC
 CLK |2       15| /RCO
  P0 |3       14| Q0
  P1 |4   74  13| Q1
  P2 |5  169  12| Q2
  P3 |6       11| Q3
/ENP |7       10| /ENT
 GND |8        9| /LOAD
     +----------+

74170

4x4-bit open-collector dual-port register file.
    +---+--+---+
 D2 |1  +--+ 16| VCC
 D3 |2       15| D1
 D4 |3       14| WA0
RA1 |4   74  13| WA1
RA0 |5  170  12| /WR
 Q4 |6       11| /RD
 Q3 |7       10| Q1
GND |8        9| Q2
    +----------+

74173

4-bit 3-state D flip-flop with reset, dual clock enables and dual output enables.
     +---+--+---+
/OE1 |1  +--+ 16| VCC
/OE2 |2       15| RST
  Q0 |3       14| D0
  Q1 |4   74  13| D1
  Q2 |5  173  12| D2
  Q3 |6       11| D3
 CLK |7       10| /CLKEN1
 GND |8        9| /CLKEN2
     +----------+

74174

6-bit D flip-flop with reset.
     +---+--+---+            +----+---+---*---+
/RST |1  +--+ 16| VCC        |/RST|CLK| D | Q |
  Q0 |2       15| Q6         +====+===+===*===+
  D0 |3       14| D5         |  0 | X | X | 0 |
  D1 |4   74  13| D4         |  1 | / | 0 | 0 |
  Q1 |5  174  12| Q4         |  1 | / | 1 | 1 |
  D2 |6       11| D3         |  1 |!/ | X | - |
  Q2 |7       10| Q3         +----+---+---*---+
 GND |8        9| CLK
     +----------+

74175

4-bit D flip-flop with complementary outputs and reset.
     +---+--+---+            +----+---+---*---+---+
/RST |1  +--+ 16| VCC        |/RST|CLK| D | Q |/Q |
  Q1 |2       15| Q4         +====+===+===*===+===+
 /Q1 |3       14| /Q4        |  0 | X | X | 0 | 1 |
  D1 |4   74  13| D4         |  1 | / | 0 | 0 | 1 |
  D2 |5  175  12| D3         |  1 | / | 1 | 1 | 0 |
 /Q2 |6       11| /Q3        |  1 |!/ | X | - | - |
  Q2 |7       10| Q3         +----+---+---*---+---+
 GND |8        9| CLK
     +----------+

74180

8-bit odd/even parity generator/checker with cascade inputs.
      +---+--+---+
   A0 |1  +--+ 14| VCC
   A1 |2       13| A7
 CASE |3   74  12| A6
 CASO |4  180  11| A5
 EVEN |5       10| A4
  ODD |6        9| A3
  GND |7        8| A2
      +----------+

74181

4-bit 16-function arithmetic logic unit (ALU)
    +---+--+---+
/B0 |1  +--+ 24| VCC
/A0 |2       23| /A1
 S3 |3       22| /B1
 S2 |4       21| /A2
 S1 |5       20| /B2
 S0 |6   74  19| /A3
CIN |7  181  18| /B3
  M |8       17| /G
/F0 |9       16| COUT
/F1 |10      15| /P
/F2 |11      14| A=B
GND |12      13| /F3
    +----------+

74182

Look-ahead carry generator Capable of anticipating a carry across four binary adders or group of adders.
Cascadable to perform full look-ahead across n-bit adders.
    +---+--+---+
/G1 |1  +--+ 16| VCC
/P1 |2       15| /P2
/G0 |3       14| /G2
/P0 |4   74  13| Cn
/G3 |5  182  12| Cn+X
/P3 |6       11| Cn+Y
 /P |7       10| /G
GND |8        9| Cn+Z
    +----------+

74183

Dual full adder.
    +---+--+---+           +---+---+---*---+---+
 1A |1  +--+ 14| VCC       | CI| A | B | S | CO|
    |2       13| 2A        +===+===+===*===+===+
 1B |3  74   12| 2B        | 0 | 0 | 0 | 0 | 0 |
1CI |4  183  11| 2CI       | 0 | 0 | 1 | 1 | 0 |
1CO |5       10| 2CO       | 0 | 1 | 0 | 1 | 0 |
 1S |6        9|           | 0 | 1 | 1 | 0 | 1 |
GND |7        8| 2S        | 1 | 0 | 0 | 1 | 0 |
    +----------+           | 1 | 0 | 1 | 0 | 1 |
                           | 1 | 1 | 0 | 0 | 1 |
                           | 1 | 1 | 1 | 1 | 1 |
                           +---+---+---*---+---+

74190

4-bit synchronous decade up/down counter with load and both carry out and ripple clock outputs.
       +---+--+---+
    P1 |1  +--+ 16| VCC
    Q1 |2       15| P0
    Q0 |3       14| CLK
/CLKEN |4   74  13| /RCLK
  D//U |5  190  12| /RCO
    Q2 |6       11| /LOAD
    Q3 |7       10| P2
   GND |8        9| P3
       +----------+

74191

4-bit synchronous binary up/down counter with load and both carry out and ripple clock outputs.
       +---+--+---+
    P1 |1  +--+ 16| VCC
    Q1 |2       15| P0
    Q0 |3       14| CLK
/CLKEN |4   74  13| /RCLK
  D//U |5  191  12| /RCO
    Q2 |6       11| /LOAD
    Q3 |7       10| P2
   GND |8        9| P3
       +----------+

74192

4-bit synchronous decade up/down counter with asynchronous load and reset, and separate up and down clocks, carry and borrow outputs.
     +---+--+---+
  P1 |1  +--+ 16| VCC
  Q1 |2       15| P0
  Q0 |3       14| RST
DOWN |4   74  13| /BORROW
  UP |5  192  12| /CARRY
  Q2 |6       11| /LOAD
  Q3 |7       10| P2
 GND |8        9| P3
     +----------+

74193

4-bit synchronous binary up/down counter with asynchronous load and reset, and separate up and down clocks. Carry and borrow outputs.
     +---+--+---+
  P1 |1  +--+ 16| VCC
  Q1 |2       15| P0
  Q0 |3       14| RST
DOWN |4   74  13| /BORROW
  UP |5  193  12| /CARRY
  Q2 |6       11| /LOAD
  Q3 |7       10| P2
 GND |8        9| P3
     +----------+


74194

4-bit bidirectional universal shift register with asynchronous reset.
     +---+--+---+            +---+---*---------------+
/RST |1  +--+ 16| VCC        | S1| S0| Function      |
   D |2       15| Q0         +===+===*===============+
  P0 |3       14| Q1         | 0 | 0 | Hold          |
  P1 |4 40194 13| Q2         | 0 | 1 | Shift right   |
  P2 |5 74194 12| Q3         | 1 | 0 | Shift left    |
  P3 |6       11| CLK        | 1 | 1 | Parallel load |
   L |7       10| S1         +---+---*---------------+
 GND |8        9| S0
     +----------+

74195

4-bit universal shift register with J-/K inputs and asynchronous reset.
     +---+--+---+
/RST |1  +--+ 16| VCC
   J |2       15| Q0
  /K |3       14| Q1
  P0 |4   74  13| Q2
  P1 |5  195  12| Q3
  P2 |6       11| /Q3
  P3 |7       10| CLK
 GND |8        9| SH//LD
     +----------+


74196

4-bit asynchronous decade counter with /2 and /5 sections, load and reset.
      +---+--+---+
/LOAD |1  +--+ 14| VCC
   Q2 |2       13| /RST
   P2 |3   74  12| Q3
   P0 |4  196  11| P3
   Q0 |5       10| P1
/CLK1 |6        9| Q1
  GND |7        8| /CLK0
      +----------+

74197

4-bit asynchronous binary counter with /2 and /8 sections, load and reset.
      +---+--+---+
/LOAD |1  +--+ 14| VCC
   Q2 |2       13| /RST
   P2 |3   74  12| Q3
   P0 |4  197  11| P3
   Q0 |5       10| P1
/CLK1 |6        9| Q1
  GND |7        8| /CLK0
      +----------+


74198

8-bit bidirectional universal shift register with asynchronous reset.
    +---+--+---+
 S0 |1  +--+ 24| VCC
  D |2       23| S1
 P0 |3       22| Q7
 Y0 |4       21| P7
 P1 |5       20| Y7
 Y1 |6   74  19| P6
 P2 |7  198  18| Y6
 Y2 |8       17| P5
 P3 |9       16| Y5
 Y3 |10      15| P4
CLK |11      14| Y4
GND |12      13| /RST
    +----------+

Pinouts of IC and Electronic Devices

7400 series TTL ICs 74100.74149

7400 series TTL ICs 74100.74149
74100-74149 74LSxxx, 74HCxxx, 74AHCxxx, 74Fxxx, 74ALSxxx


74107

Dual negative-edge-triggered J-K flip-flops with reset.
    +---+--+---+             +---+---+----+----*---+---+
 1J |1  +--+ 14| VCC         | J | K |/CLK|/RST| Q |/Q |
/1Q |2       13| /1RST       +===+===+====+====*===+===+
 1Q |3   74  12| /1CLK       | X | X |  X |  0 | 0 | 1 |
 1K |4  107  11| 2K          | 0 | 0 |  \ |  1 | - | - |
 2Q |5       10| /2RST       | 0 | 1 |  \ |  1 | 0 | 1 |
/2Q |6        9| /2CLK       | 1 | 0 |  \ |  1 | 1 | 0 |
GND |7        8| 2J          | 1 | 1 |  \ |  1 |/Q | Q |
    +----------+             | X | X | !\ |  1 | - | - |
                             +---+---+----+----*---+---+

74109

Dual J-/K flip-flops with set and reset.
      +---+--+---+           +---+---+---+----+----*---+---+
/1RST |1  +--+ 16| VCC       | J |/K |CLK|/SET|/RST| Q |/Q |
   1J |2       15| /2RST     +===+===+===+====+====*===+===+
  /1K |3       14| 2J        | X | X | X |  0 |  0 | 1 | 1 |
 1CLK |4   74  13| /2K       | X | X | X |  0 |  1 | 1 | 0 |
/1SET |5  109  12| 2CLK      | X | X | X |  1 |  0 | 0 | 1 |
   1Q |6       11| /2SET     | 0 | 0 | / |  1 |  1 | 0 | 1 |
  /1Q |7       10| 2Q        | 0 | 1 | / |  1 |  1 | - | - |
  GND |8        9| /2Q       | 1 | 0 | / |  1 |  1 |/Q | Q |
      +----------+           | 1 | 1 | / |  1 |  1 | 1 | 0 |
                             | X | X |!/ |  1 |  1 | - | - |
                             +---+---+---+----+----*---+---+

74112

Dual negative-edge-triggered J-K flip-flops with set and reset.
      +---+--+---+           +---+---+----+----+----*---+---+
/1CLK |1  +--+ 16| VCC       | J | K |/CLK|/SET|/RST| Q |/Q |
   1K |2       15| /1RST     +===+===+====+====+====*===+===+
   1J |3       14| /2RST     | X | X |  X |  0 |  0 | 0 | 0 |
/1SET |4   74  13| /2CLK     | X | X |  X |  0 |  1 | 1 | 0 |
   1Q |5  112  12| 2K        | X | X |  X |  1 |  0 | 0 | 1 |
  /1Q |6       11| 2J        | 0 | 0 |  \ |  1 |  1 | - | - |
  /2Q |7       10| /2SET     | 0 | 1 |  \ |  1 |  1 | 0 | 1 |
  GND |8        9| 2Q        | 1 | 0 |  \ |  1 |  1 | 1 | 0 |
      +----------+           | 1 | 1 |  \ |  1 |  1 |/Q | Q |
                             | X | X | !\ |  1 |  1 | - | - |
                             +---+---+----+----+----*---+---+


74113

Dual negative-edge-triggered J-K flip-flop with set.
      +---+--+---+           +---+---+----+----*---+---+
/1CLK |1  +--+ 14| VCC       | J | K |/CLK|/SET| Q |/Q |
   1K |2       13| /2CLK     +===+===+====+====*===+===+
   1J |3  74   12| 2K        | X | X |  X |  0 | 1 | 0 |
/1SET |4  113  11| 2J        | X | X |  X |  1 | 0 | 1 |
   1Q |5       10| /2SET     | 0 | 0 |  \ |  1 | - | - |
  /1Q |6        9| 2Q        | 0 | 1 |  \ |  1 | 0 | 1 |
  GND |7        8| /2Q       | 1 | 0 |  \ |  1 | 1 | 0 |
      +----------+           | 1 | 1 |  \ |  1 |/Q | Q |
                             | X | X | !\ |  1 | - | - |
                             +---+---+----+----*---+---+

74114

Dual negative-edge-triggered J-K flip-flop with set, common clock and common reset.
      +---+--+---+           +---+---+----+----+----*---+---+
 /RST |1  +--+ 14| VCC       | J | K |/CLK|/SET|/RST| Q |/Q |
   1K |2       13| /CLK      +===+===+====+====+====*===+===+
   1J |3  74   12| 2K        | X | X |  X |  0 |  0 | ? | ? |
/1SET |4  114  11| 2J        | X | X |  X |  0 |  1 | 1 | 0 |
   1Q |5       10| /2SET     | X | X |  X |  1 |  0 | 0 | 1 |
  /1Q |6        9| 2Q        | 0 | 0 |  \ |  1 |  1 | - | - |
  GND |7        8| /2Q       | 0 | 1 |  \ |  1 |  1 | 0 | 1 |
      +----------+           | 1 | 0 |  \ |  1 |  1 | 1 | 0 |
                             | 1 | 1 |  \ |  1 |  1 |/Q | Q |
                             | X | X | !\ |  1 |  1 | - | - |
                             +---+---+----+----+----*---+---+


74121

Monostable multivibrator with Schmitt-trigger inputs.
Programmable output pulse width from 40 ns to 20 seconds.
     +---+--+---+
  /Q |1  +--+ 14| VCC
     |2       13|
/TR1 |3   74  12|
/TR2 |4  121  11| RCext
  TR |5       10| Cext
   Q |6        9| Rint
 GND |7        8|
     +----------+

74122

Retriggerable monostable multivibrator with overriding reset and integrated 10k timing resistor.
     +---+--+---+
/TR1 |1  +--+ 14| VCC
/TR2 |2       13| RCext
 TR1 |3   74  12|
 TR2 |4  122  11| Cext
/RST |5       10|
  /Q |6        9| Rint
 GND |7        8| Q
     +----------+

74123

Dual retriggerable monostable multivibrators with overriding reset.
       +---+--+---+
  /1TR |1  +--+ 16| VCC
   1TR |2       15| 1RCext
 /1RST |3       14| 1Cext
   /1Q |4   74  13| 1Q
    2Q |5  123  12| /2Q
 2Cext |6       11| /2RST
2RCext |7       10| 2TR
   GND |8        9| /2TR
       +----------+

74125

Quad 3-state noninverting buffer with active low enables.
     +---+--+---+            +---+---*---+
/1OE |1  +--+ 14| VCC        | A |/OE| Y |
  1A |2       13| /4OE       +===+===*===+
  1Y |3   74  12| 4A         | 0 | 0 | 0 |
/2OE |4  125  11| 4Y         | 1 | 0 | 1 |
  2A |5       10| /3OE       | X | 1 | Z |
  2Y |6        9| 3A         +---+---*---+
 GND |7        8| 3Y
     +----------+

74126

Quad 3-state noninverting buffer with active high enables.
    +---+--+---+             +---+---*---+
1OE |1  +--+ 14| VCC         | A | OE| Y |
 1A |2       13| 4OE         +===+===*===+
 1Y |3   74  12| 4A          | X | 0 | Z |
2OE |4  126  11| 4Y          | 0 | 1 | 0 |
 2A |5       10| 3OE         | 1 | 1 | 1 |
 2Y |6        9| 3A          +---+---*---+
GND |7        8| 3Y
    +----------+

74128

Quad 2-input NOR gates/line drivers.
    +---+--+---+             +---+---*---+           ___
/1Y |1  +--+ 14| VCC         | A | B |/Y |      /Y = A+B
 1A |2       13| /4Y         +===+===*===+
 1B |3       12| 4B          | 0 | 0 | 1 |
/2Y |4  7402 11| 4A          | 0 | 1 | 0 |
 2A |5       10| /3Y         | 1 | 0 | 0 |
 2B |6        9| 3B          | 1 | 1 | 0 |
GND |7        8| 3A          +---+---*---+
    +----------+

74131

1-of-8 inverting decoder/demultiplexer with address register.
     +---+--+---+
  S0 |1  +--+ 16| VCC
  S1 |2       15| /Y0
  S2 |3       14| /Y1
 CLK |4   74  13| /Y2
/EN2 |5  131  12| /Y3
 EN1 |6       11| /Y4
 /Y7 |7       10| /Y5
 GND |8        9| /Y6
     +----------+

74132

Quad 2-input NAND gates with schmitt-trigger inputs.
0.8V typical input hysteresis at VCC=+5V.
    +---+--+---+             +---+---*---+           __
 1A |1  +--+ 14| VCC         | A | B |/Y |      /Y = AB
 1B |2       13| 4B          +===+===*===+
/1Y |3       12| 4A          | 0 | 0 | 1 |
 2A |4 74132 11| /4Y         | 0 | 1 | 1 |
 2B |5       10| 3B          | 1 | 0 | 1 |
/2Y |6        9| 3A          | 1 | 1 | 0 |
GND |7        8| /3Y         +---+---*---+
    +----------+

74133

13-input NAND gate.
    +---+--+---+                 _____________
  A |1  +--+ 16| VCC        /Y = ABCDEFGHIJKLM
  B |2       15| M
  C |3       14| L
  D |4   74  13| K
  E |5  133  12| J
  F |6       11| I
  G |7       10| H
GND |8        9| /Y
    +----------+

74136

Quad 2-input open-collector XOR gates.
    +---+--+---+             +---+---*---+                    _   _
 1A |1  +--+ 14| VCC         | A | B | Y |       Y = A$B = (A.B)+(A.B)
 1B |2       13| 4B          +===+===*===+
 1Y |3       12| 4A          | 0 | 0 | 0 |
 2A |4 74136 11| 4Y          | 0 | 1 | Z |
 2B |5       10| 3B          | 1 | 0 | Z |
 2Y |6        9| 3A          | 1 | 1 | 0 |
GND |7        8| 3Y          +---+---*---+
    +----------+

74137

1-of-8 inverting decoder/demultiplexer with address latches.
     +---+--+---+
  S0 |1  +--+ 16| VCC
  S1 |2       15| /Y0
  S2 |3       14| /Y1
 /LE |4   74  13| /Y2
/EN2 |5  137  12| /Y3
 EN1 |6       11| /Y4
 /Y7 |7       10| /Y5
 GND |8        9| /Y6
     +----------+

74138

1-of-8 inverting decoder/demultiplexer.
     +---+--+---+            +---+----+----+---+---+---*---+---+---+---+
  S0 |1  +--+ 16| VCC        |EN1|/EN2|/EN3| S2| S1| S0|/Y0|/Y1|...|/Y7|
  S1 |2       15| /Y0        +===+====+====+===+===+===*===+===+===+===+
  S2 |3       14| /Y1        | 0 | X  |  X | X | X | X | 1 | 1 | 1 | 1 |
/EN3 |4   74  13| /Y2        | 1 | 1  |  X | X | X | X | 1 | 1 | 1 | 1 |
/EN2 |5  138  12| /Y3        | 1 | 0  |  1 | X | X | X | 1 | 1 | 1 | 1 |
 EN1 |6       11| /Y4        | 1 | 0  |  0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 |
 /Y7 |7       10| /Y5        | 1 | 0  |  0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 |
 GND |8        9| /Y6        | 1 | 0  |  0 | . | . | . | 1 | 1 | . | 1 |
     +----------+            | 1 | 0  |  0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
                             +---+----+----+---+---+---*---+---+---+---+

74139

Dual 1-of-4 inverting decoder/demultiplexer.
     +---+--+---+            +---+---+---*---+---+---+---+
/1EN |1  +--+ 16| VCC        |/EN| S1| S0|/Y0|/Y1|/Y2|/Y3|
 1S0 |2       15| /2EN       +===+===+===*===+===+===+===+
 1S1 |3       14| 2S0        | 1 | X | X | 1 | 1 | 1 | 1 |
/1Y0 |4   74  13| 2S1        | 0 | 0 | 0 | 0 | 1 | 1 | 1 |
/1Y1 |5  139  12| /2Y0       | 0 | 0 | 1 | 1 | 0 | 1 | 1 |
/1Y2 |6       11| /2Y1       | 0 | 1 | 0 | 1 | 1 | 0 | 1 |
/1Y3 |7       10| /2Y2       | 0 | 1 | 1 | 1 | 1 | 1 | 0 |
 GND |8        9| /2Y3       +---+---+---*---+---+---+---+
     +----------+


74140

Dual 4-input NAND gates/50R line drivers.
    +---+--+---+             +---+---+---+---*---+        ____
 1A |1  +--+ 14| VCC         | A | B | C | D |/Y |   /Y = ABCD
 1B |2       13| 2D          +===+===+===+===*===+
    |3   74  12| 2C          | 0 | X | X | X | 1 |
 1C |4  140  11|             | 1 | 0 | X | X | 1 |
 1D |5       10| 2B          | 1 | 1 | 0 | X | 1 |
/1Y |6        9| 2A          | 1 | 1 | 1 | 0 | 1 |
GND |7        8| /2Y         | 1 | 1 | 1 | 1 | 0 |
    +----------+             +---+---+---+---*---+

74141

1-of-10 inverting decoder/demultiplexer.
    +---+--+---+             +---+---+---+---*---+---+---+---+
/Y8 |1  +--+ 16| /Y0         | S3| S2| S1| S0|/Y0|/Y1|...|/Y9|
/Y9 |2       15| /Y1         +===+===+===+===*===+===+===+===+
 S0 |3       14| /Y5         | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 |
 S3 |4   74  13| /Y4         | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 |
VCC |5  141  12| GND         | . | . | . | . | 1 | 1 | . | 1 |
 S1 |6       11| /Y6         | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |
 S2 |7       10| /Y7         | 1 | 0 | 1 | X | 1 | 1 | 1 | 1 |
/Y2 |8        9| /Y3         | 1 | 1 | X | X | 1 | 1 | 1 | 1 |
    +----------+             +---+---+---+---*---+---+---+---+


74145

1-of-10 open-collector inverting decoder/demultiplexer.
    +---+--+---+             +---+---+---+---*---+---+---+---+
/Y0 |1  +--+ 16| VCC         | S3| S2| S1| S0|/Y0|/Y1|...|/Y9|
/Y1 |2       15| S0          +===+===+===+===*===+===+===+===+
/Y2 |3       14| S1          | 0 | 0 | 0 | 0 | 0 | Z | Z | Z |
/Y3 |4   74  13| S2          | 0 | 0 | 0 | 1 | Z | 0 | Z | Z |
/Y4 |5  145  12| S3          | . | . | . | . | Z | Z | . | Z |
/Y5 |6       11| /Y9         | 1 | 0 | 0 | 1 | Z | Z | Z | 0 |
/Y6 |7       10| /Y8         | 1 | 0 | 1 | X | Z | Z | Z | Z |
GND |8        9| /Y7         | 1 | 1 | X | X | Z | Z | Z | Z |
    +----------+             +---+---+---+---*---+---+---+---+

74147

10-to-4 line inverting priority encoder.
    +---+--+---+
/A4 |1  +--+ 16| VCC
/A5 |2       15|
/A6 |3       14| Y3
/A7 |4   74  13| /A3
/A8 |5  147  12| /A2
 Y2 |6       11| /A1
 Y1 |7       10| /A9
GND |8        9| Y0
    +----------+


74148

8-to-3 line inverting priority encoder with cascade inputs.
    +---+--+---+
/A4 |1  +--+ 16| VCC
/A5 |2       15| /EO
/A6 |3       14| /GS
/A7 |4   74  13| /A3
/EI |5  148  12| /A2
 Y2 |6       11| /A1
 Y1 |7       10| /A0
GND |8        9| Y0
    +----------+
Pinouts of IC and Electronic Devices

7450-7499 74LSxxx, 74HCxxx, 74AHCxxx, 74Fxxx, 74ALSxxx

7400 series TTL IC's: 7450...7499
7450-7499 74LSxxx, 74HCxxx, 74AHCxxx, 74Fxxx, 74ALSxxx



7451

2-wide 2-input and 2-wide 3-input AND-NOR gates.
    +---+--+---+                  _____________________
 1A |1  +--+ 14| VCC        /1Y = (1A.1B.1C)+(1D.1E.1F)
 2A |2       13| 1B
 2B |3       12| 1C               _______________
 2C |4  7451 11| 1D         /2Y = (2A.2B)+(2C.2D)
 2D |5       10| 1E
/2Y |6        9| 1F
GND |7        8| /1Y
    +----------+

7454

4-wide 2/3-input AND-NOR gate.
    +---+--+---+                 ___________________________
  A |1  +--+ 14| VCC        /Y = (A.B)+(C.D.E)+(F.G.H)+(J.K)
  B |2       13| K
  C |3       12| J
  D |4  7454 11| H
  E |5       10| G
 /Y |6        9| F
GND |7        8|
    +----------+

7455

2-wide 4-input AND-NOR gate.
    +---+--+---+                 ___________________
  A |1  +--+ 14| VCC        /Y = (A.B.C.D)+(E.F.G.H)
  B |2       13| H
  C |3       12| G
  D |4  7455 11| F
    |5       10| E
    |6        9|
GND |7        8| /Y
    +----------+


7457

Frequency divider.
Can generate one second timing pulses from 60 Hz. Two '57 devices may be interconnected to give frequency division of 3600 to 1, 1800 to 1, 900 to 1, etc. Features a reset pin that is common to all three counters.
     +---+--+---+
CLKB |1  +--+  8| QC
 VCC |2        7| QB
  QA |3  7457  6| RST
 GND |4        5| CLKA
     +----------+

7458

2-wide 2-input and 2-wide 3-input AND-OR gates.
    +---+--+---+
 1A |1  +--+ 14| VCC         1Y = (1A.1B.1C)+(1D.1E.1F)
 2A |2       13| 1B
 2B |3       12| 1C
 2C |4  7458 11| 1D          2Y = (2A.2B)+(2C.2D)
 2D |5       10| 1E
 2Y |6        9| 1F
GND |7        8| 1Y
    +----------+

7472

J-K flip-flop with triple ANDed J an K inputs, set and reset.
     +---+--+---+            +--------+--------+---+----+----*---+---+
     |1  +--+ 14| VCC        |J1.J2.J3|K1.K2.K3|CLK|/SET|/RST| Q |/Q |
/RST |2       13| /SET       +========+========+===+====+====*===+===+
  J1 |3       12| CLK        |    X   |    X   | X |  0 |  0 | ? | ? |
  J2 |4  7472 11| K3         |    X   |    X   | X |  0 |  1 | 1 | 0 |
  J3 |5       10| K2         |    X   |    X   | X |  1 |  0 | 0 | 1 |
  /Q |6        9| K1         |    0   |    0   | / |  1 |  1 | - | - |
 GND |7        8| Q          |    0   |    1   | / |  1 |  1 | 0 | 1 |
     +----------+            |    1   |    0   | / |  1 |  1 | 1 | 0 |
                             |    1   |    1   | / |  1 |  1 |/Q | Q |
                             |    X   |    X   |!/ |  1 |  1 | - | - |
                             +--------+--------+---+----+----*---+---+

7473

Dual negative-edge-triggered J-K flip-flop with reset.
      +---+--+---+           +---+---+----+----*---+---+
/1CLK |1  +--+ 14| 1J        | J | K |/CLK|/RST| Q |/Q |
/1RST |2       13| /1Q       +===+===+====+====*===+===+
   1K |3       12| 1Q        | X | X |  X |  0 | 0 | 1 |
  VCC |4  7473 11| GND       | 0 | 0 |  \ |  1 | - | - |
/2CLK |5       10| 2K        | 0 | 1 |  \ |  1 | 0 | 1 |
/2RST |6        9| 2Q        | 1 | 0 |  \ |  1 | 1 | 0 |
   2J |7        8| /2Q       | 1 | 1 |  \ |  1 |/Q | Q |
      +----------+           | X | X | !\ |  1 | - | - |
                             +---+---+----+----*---+---+

7474

Dual D flip-flop with set and reset.
      +---+--+---+           +---+---+----+----*---+---+
/1RST |1  +--+ 14| VCC       | D |CLK|/SET|/RST| Q |/Q |
   1D |2       13| /2RST     +===+===+====+====*===+===+
 1CLK |3       12| 2D        | X | X |  0 |  0 | 1 | 1 |
/1SET |4  7474 11| 2CLK      | X | X |  0 |  1 | 1 | 0 |
   1Q |5       10| /2SET     | X | X |  1 |  0 | 0 | 1 |
  /1Q |6        9| 2Q        | 0 | / |  1 |  1 | 0 | 1 |
  GND |7        8| /2Q       | 1 | / |  1 |  1 | 1 | 1 |
      +----------+           | X |!/ |  1 |  1 | - | - |
                             +---+---+----+----*---+---+

7475

Dual 2-bit transparent latches with complementary outputs.
     +---+--+---+
/1Q1 |1  +--+ 16| 1Q1
 1D1 |2       15| 1Q2
 1D2 |3       14| /1Q2
 2LE |4       13| 1LE
 VCC |5  7475 12| GND
 2D1 |6       11| /2Q1
 2D2 |7       10| 2Q1
/2Q2 |8        9| 2Q2
     +----------+

7476

Dual J-K flip-flops with set and reset.
      +---+--+---+           +---+---+---+----+----*---+---+
 1CLK |1  +--+ 16| 1K        | J | K |CLK|/SET|/RST| Q |/Q |
/1SET |2       15| 1Q        +===+===+===+====+====*===+===+
/1RST |3       14| /1Q       | X | X | X |  0 |  0 | 0 | 0 |
   1J |4       13| GND       | X | X | X |  0 |  1 | 1 | 0 |
  VCC |5  7476 12| 2K        | X | X | X |  1 |  0 | 0 | 1 |
 2CLK |6       11| 2Q        | 0 | 0 | / |  1 |  1 | - | - |
/2SET |7       10| /2Q       | 0 | 1 | / |  1 |  1 | 0 | 1 |
/2RST |8        9| 2J        | 1 | 0 | / |  1 |  1 | 1 | 0 |
      +----------+           | 1 | 1 | / |  1 |  1 |/Q | Q |
                             | X | X |!/ |  1 |  1 | - | - |
                             +---+---+---+----+----*---+---+

7478

Dual negative-edge-triggered J-K flip-flops with common clock, set and common reset.
      +---+--+---+           +---+---+----+----+----*---+---+
 /CLK |1  +--+ 14| 1K        | J | K |/CLK|/SET|/RST| Q |/Q |
/1SET |2       13| 1Q        +===+===+====+====+====*===+===+
   1J |3       12| /1Q       | X | X |  X |  0 |  0 | ? | ? |
  VCC |4  7478 11| GND       | X | X |  X |  0 |  1 | 1 | 0 |
 /RST |5       10| 2J        | X | X |  X |  1 |  0 | 0 | 1 |
/2SET |6        9| /2Q       | 0 | 0 |  \ |  1 |  1 | - | - |
   2K |7        8| 2Q        | 0 | 1 |  \ |  1 |  1 | 0 | 1 |
      +----------+           | 1 | 0 |  \ |  1 |  1 | 1 | 0 |
                             | 1 | 1 |  \ |  1 |  1 |/Q | Q |
                             | X | X | !\ |  1 |  1 | - | - |
                             +---+---+----+----+----*---+---+

7483

4-bit binary full adder with fast carry.
    +---+--+---+
 A4 |1  +--+ 16| B4          S=A+B+CIN
 S3 |2       15| S4
 A3 |3       14| COUT
 B3 |4       13| CIN
VCC |5  7483 12| GND
 S2 |6       11| B1
 B2 |7       10| A1
 A2 |8        9| S1
    +----------+

7485

4-bit noninverting magnitude comparator with cascade inputs.
     +---+--+---+
  B3 |1  +--+ 16| VCC
IA<B |2       15| A3
IA=B |3       14| B2
IA>B |4       13| A2
OA>B |5  7485 12| A1
OA=B |6       11| B1
OA<B |7       10| A0
 GND |8        9| B0
     +----------+

7486

Quad 2-input XOR gates.
    +---+--+---+             +---+---*---+                    _   _
 1A |1  +--+ 14| VCC         | A | B | Y |       Y = A$B = (A.B)+(A.B)
 1B |2       13| 4B          +===+===*===+
 1Y |3       12| 4A          | 0 | 0 | 0 |
 2A |4  7486 11| 4Y          | 0 | 1 | 1 |
 2B |5       10| 3B          | 1 | 0 | 1 |
 2Y |6        9| 3A          | 1 | 1 | 0 |
GND |7        8| 3Y          +---+---*---+
    +----------+


7490

4-bit asynchronous decade counter with /2 and /5 sections, set(9) and reset.
      +---+--+---+
/CLK1 |1  +--+ 14| /CLK0
 RST1 |2       13|
 RST2 |3       12| Q0
      |4  7490 11| Q3
  VCC |5       10| GND
 SET1 |6        9| Q1
 SET2 |7        8| Q2
      +----------+

7491

8-bit serial-in serial-out shift register with two AND gated serial inputs and complementary outputs.
    +---+--+---+
    |1  +--+ 14| /Q7
    |2       13| Q7
    |3       12| D
    |4  7491 11| E
VCC |5       10| GND
    |6        9| CLK
    |7        8|
    +----------+


7492

4-bit asynchronous divide-by-twelve counter with /2 and /6 sections and reset.
      +---+--+---+
/CLK1 |1  +--+ 14| /CLK0
      |2       13|
      |3       12| Q0
      |4  7492 11| Q3
  VCC |5       10| GND
 RST1 |6        9| Q1
 RST2 |7        8| Q2
      +----------+

7493

4-bit asynchronous binary counter with /2 and /8 sections and reset.
      +---+--+---+
/CLK1 |1  +--+ 14| /CLK0
 RST1 |2       13|
 RST2 |3       12| Q0
      |4  7493 11| Q3
  VCC |5       10| GND
      |6        9| Q1
      |7        8| Q2
      +----------+


7495

4-bit universal shift register with separate shift and parallel-load clocks.
       +---+--+---+
     D |1  +--+ 14| VCC
    P0 |2       13| Q0
    P1 |3       12| Q1
    P2 |4  7495 11| Q2
    P3 |5       10| Q3
LD//SH |6        9| SHCLK
   GND |7        8| LDCLK
       +----------+

7496

5-bit shift register with asynchronous reset and asynchronous preset inputs.
    +---+--+---+
CLK |1  +--+ 16| /RST
 P0 |2       15| Q0
 P1 |3       14| Q1
 P2 |4       13| Q2
VCC |5  7496 12| GND
 P3 |6       11| Q3
 P4 |7       10| Q4
 PE |8        9| D
    +----------+


7497

6-bit synchronous binary rate multiplier.
Can perform fixed-rate or variable-rate frequency division. Output frequency is equal to input frequency multiplied by the rate input M and divided by 64.
      +---+--+---+
   B1 |1  +--+ 16| VCC
   B4 |2       15| B3
   B5 |3       14| B2
   B0 |4       13| RST
    Z |5  7497 12| U/CAS
    Y |6       11| ENin
ENout |7       10| STRB
  GND |8        9| CLK
      +----------+

Pinouts of IC and Electronic Devices